This patch makes snd_dmaengine_pcm_register with rockchip_dmaengine_pcm_config,
which configure the parameters of period and buffer match to rockchip DMAC.
=======================
without rockchip_dmaengine_pcm_config, and test with command -
aplay -D hw:0,0 /tmp/a, there are the error dump:
[ 134.899396] dma-pl330 ffb20000.dma-controller: fill_queue:2251 Bad Desc(7)
[ 134.906270] dma-pl330 ffb20000.dma-controller: fill_queue:2251 Bad Desc(8)
[ 134.913141] dma-pl330 ffb20000.dma-controller: fill_queue:2251 Bad Desc(9)
And bellow sound from DMA debugger:
"I debugged it a little and it looks like what is happening is that requests
which aren't a multiple of burst size * burst length are coming in. Right
now the i2s block is setting a burst size of 4 and burst length of 4, but
the dmaengine code has no idea about this restriction. I was able to
eliminate the messages by changing burst length to 1 in the i2s driver.
This fix would always work as long as we're sending a multiple of 4 bytes
(which so far seems to be the case)"
This patch can make the length of dma buffer is aligned to a multiple of burst size
and burst length.