RE: [PATCH 1/5] KVM: nVMX: Make nested control MSRs per-cpu.

[Zhang, Yang Z]

Wincy Van wrote on 2015-01-16:
> To enable nested apicv support, we need per-cpu vmx control MSRs:
>   1. If in-kernel irqchip is enabled, we can enable nested
>      posted interrupt, we should set posted intr bit in the
>      nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
>      we can not enable nested posted interrupt, the posted intr bit in
>      the nested_vmx_pinbased_ctls_high will be cleared.
> Since there would be different settings about in-kernel irqchip
> between VMs, different nested control MSRs are needed.

I'd suggest you to check irqchip_in_kernel() instead moving the whole ctrl msr to per vcpu.

Best regards,
Yang