Re: [PATCH 1/2] i2c: tegra: Maintain CPU endianness

[Alexandre Courbot]

On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
<thierry.reding@xxxxxxxxx> wrote:
> On Tue, Jan 20, 2015 at 03:22:25PM +0300, Dmitry Osipenko wrote:
>> Support CPU BE mode by adding endianness conversion for memcpy interactions.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
>> ---
>>  drivers/i2c/busses/i2c-tegra.c | 3 +++
>>  1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
>> index 28b87e6..e0d3ef1 100644
>> --- a/drivers/i2c/busses/i2c-tegra.c
>> +++ b/drivers/i2c/busses/i2c-tegra.c
>> @@ -286,6 +286,7 @@ static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
>>       if (rx_fifo_avail > 0 && buf_remaining > 0) {
>>               BUG_ON(buf_remaining > 3);
>>               val = i2c_readl(i2c_dev, I2C_RX_FIFO);
>> +             val = cpu_to_le32(val);
>
> Should this not technically be le32_to_cpu() since the data originates
> from the I2C controller?
>
>>               memcpy(buf, &val, buf_remaining);
>>               buf_remaining = 0;
>>               rx_fifo_avail--;
>> @@ -343,7 +344,9 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
>>        */
>>       if (tx_fifo_avail > 0 && buf_remaining > 0) {
>>               BUG_ON(buf_remaining > 3);
>> +             val = 0;
>
> Why does this have to be initialized to 0 now?

I suspect this is because we are going to memcpy less than 4 bytes
into it, but I cannot figure out how that memcpy if guaranteed to
produce the expected result for both endiannesses.
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