Re: [PATCH v3 00/11] powerpc8xx: Further optimisation of TLB handling
From: Scott Wood
Date: Tue Feb 03 2015 - 12:18:04 EST
On Tue, 2015-02-03 at 12:38 +0100, Christophe Leroy wrote:
> This patchset provides a further optimisation of TLB handling in the 8xx.
> Main changes are based on:
> - Using processor handling of PGD/PTE Validity bits instead of testing ourselves
> the entries validity
> - Aligning PGD address to allow direct bit manipulation
> - Not saving registers like CR when not needed
>
> It also adds support to any TASK_SIZE
Please respin with just the changes that haven't already been applied to
my next branch.
-Scott
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/