Re: [PATCH 1/3] perf, x86: Add new cache events table for Haswell

[Peter Zijlstra]

On Tue, Feb 10, 2015 at 09:11:35AM -0800, Andi Kleen wrote:

> > Now the other tables create little helpers like:
> > 
> > #define HSW_DMND_READ	(HSW_DMND_DATA_RD)
> > #define HSW_DMND_WRITE	(HSW_DMND_RFO)
> > 
> > #define HSW_L3_ACCESS	(HSW_ANY_RESPONSE)
> > #define HSW_L3_MISS	(HSW_L3_MISS)
> > 
> > And compose the tables values using those:
> > 
> > 	HSW_DMND_READ|HSW_L3_ACCESS
> > 
> > Please do so here too.
> 
> I'm trying to stay with the official documented bit names. No such bit names exist.
> If we make up our own names nobody else can read it anymore.

Well, its a simple matter of looking up the bit definitions; we define
those helpers in terms of the official names after all.

By having the 4 helpers {r,w}x{access,miss} you avoid some repetition
and decrease the room for mistakes.

> > Now; when comparing these value to the SNB for example I note that you
> > include ANY_SNOOP and SUPPLIER_NONE in L3_ACCESS, SNB and other do not,
> > please explain.
> 
> You're supposed to set a snoop and supplier qualifier.
> AFAIK SNB should set them too. It may work without them due to some
> quirk.

OK, then we should fix the others. Thanks.
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