Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found

[Sascha Hauer]

On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote:
> On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote:
> > On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote:
> > > If no best divider is normally found, we will try to use the maximum divider.
> > > We should not set the parent clock rate to be 1Hz by force for being rounded.
> > > Instead, we should take the maximum divider as a base and calculate a correct
> > > parent clock rate for being rounded.
> > 
> > Please add an explanation why you think the current code is wrong and
> > what this actually fixes, maybe an example?
> 
> The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on
> the MX6DL SabreSD board.
> 
> These are the clock tree summaries with or without the patch applied:
> 1) With the patch applied:
> pll5_bypass_src                       1            1    24000000          0 0
>    pll5                               1            1   844800048          0 0
>       pll5_bypass                     1            1   844800048          0 0
>          pll5_video                   1            1   844800048          0 0
>             pll5_post_div             1            1   211200012          0 0
>                pll5_video_div           1            1   211200012        0 0
>                   ipu1_di0_pre_sel           1            1   211200012   0 0
>                      ipu1_di0_pre           1            1    26400002    0 0
>                         ipu1_di0_sel           1            1    26400002 0 0
>                            ipu1_di0           1            1    26400002  0 0
> 
> 2) Without the patch applied:
> pll5_bypass_src                       1            1    24000000          0 0
>    pll5                               1            1   648000000          0 0
>       pll5_bypass                     1            1   648000000          0 0
>          pll5_video                   1            1   648000000          0 0
>             pll5_post_div             1            1   162000000          0 0
>                pll5_video_div           1            1    40500000        0 0
>                   ipu1_di0_pre_sel           1            1    40500000   0 0
>                      ipu1_di0_pre           1            1    20250000    0 0
>                         ipu1_di0_sel           1            1    20250000 0 0
>                            ipu1_di0           1            1    20250000  0 0

This seems to be broken since:

| commit b11d282dbea27db1788893115dfca8a7856bf205
| Author: Tomi Valkeinen <tomi.valkeinen@xxxxxx>
| Date:   Thu Feb 13 12:03:59 2014 +0200
| 
|     clk: divider: fix rate calculation for fractional rates

This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted
in a lower frequency than clk_round_rate(rate) returned.

Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to
the rest of the divider. Maybe this should be a simple rate * i now, but
I'm unsure what side effects this has.

I think your patch only fixes the behaviour in your case by accident,
it's not a correct fix for this issue.

Sascha

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