Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found

[Travis]

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On Feb 12, 2015 8:58 PM, Liu Ying <Ying.Liu@xxxxxxxxxxxxx> wrote:
>
> On Thu, Feb 12, 2015 at 10:06:27PM +0800, Liu Ying wrote: 
> > On Thu, Feb 12, 2015 at 02:41:31PM +0100, Sascha Hauer wrote: 
> > > On Thu, Feb 12, 2015 at 12:56:46PM +0000, Russell King - ARM Linux wrote: 
> > > > On Thu, Feb 12, 2015 at 01:24:05PM +0100, Sascha Hauer wrote: 
> > > > > On Thu, Feb 12, 2015 at 06:39:45PM +0800, Liu Ying wrote: 
> > > > > > On Thu, Feb 12, 2015 at 10:33:56AM +0100, Sascha Hauer wrote: 
> > > > > > > On Thu, Feb 12, 2015 at 02:01:24PM +0800, Liu Ying wrote: 
> > > > > > > > If no best divider is normally found, we will try to use the maximum divider. 
> > > > > > > > We should not set the parent clock rate to be 1Hz by force for being rounded. 
> > > > > > > > Instead, we should take the maximum divider as a base and calculate a correct 
> > > > > > > > parent clock rate for being rounded. 
> > > > > > > 
> > > > > > > Please add an explanation why you think the current code is wrong and 
> > > > > > > what this actually fixes, maybe an example? 
> > > > > > 
> > > > > > The MIPI DSI panel's pixel clock rate is 26.4MHz and it's derived from PLL5 on 
> > > > > > the MX6DL SabreSD board. 
> > > > > > 
> > > > > > These are the clock tree summaries with or without the patch applied: 
> > > > > > 1) With the patch applied: 
> > > > > > pll5_bypass_srcÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 24000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂ pll5ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 844800048ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂ pll5_bypassÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 844800048ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂ pll5_videoÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 844800048ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂ pll5_post_divÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 211200012ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ pll5_video_divÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 211200012ÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_pre_selÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 211200012ÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_preÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 26400002ÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_selÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 26400002 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0ÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 26400002Â 0 0 
> > > > > > 
> > > > > > 2) Without the patch applied: 
> > > > > > pll5_bypass_srcÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 24000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂ pll5ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 648000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂ pll5_bypassÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 648000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂ pll5_videoÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 648000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂ pll5_post_divÂÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂ 162000000ÂÂÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ pll5_video_divÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 40500000ÂÂÂÂÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_pre_selÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 40500000ÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_preÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 20250000ÂÂÂ 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0_selÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 20250000 0 0 
> > > > > >ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ ipu1_di0ÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂÂÂÂÂÂÂÂÂ 1ÂÂÂ 20250000Â 0 0 
> > > > > 
> > > > > This seems to be broken since: 
> > > > > 
> > > > > | commit b11d282dbea27db1788893115dfca8a7856bf205 
> > > > > | Author: Tomi Valkeinen <tomi.valkeinen@xxxxxx> 
> > > > > | Date:ÂÂ Thu Feb 13 12:03:59 2014 +0200 
> > > > > | 
> > > > > |ÂÂÂÂ clk: divider: fix rate calculation for fractional rates 
> > > > > 
> > > > > This patch fixed a case when clk_set_rate(clk_round_rate(rate)) resulted 
> > > > > in a lower frequency than clk_round_rate(rate) returned. 
> > > > > 
> > > > > Since then the MULT_ROUND_UP in clk_divider_bestdiv() is inconsistent to 
> > > > > the rest of the divider. Maybe this should be a simple rate * i now, but 
> > > > > I'm unsure what side effects this has. 
> > > > > 
> > > > > I think your patch only fixes the behaviour in your case by accident, 
> > > > > it's not a correct fix for this issue. 
> > > > 
> > > > Well, it's defined that: 
> > > > 
> > > > new_rate = clk_round_rate(clk, rate); 
> > > > 
> > > > returns the rate which you would get if you did: 
> > > > 
> > > > clk_set_rate(clk, rate); 
> > > > new_rate = clk_get_rate(clk); 
> > > > 
> > > > The reasoning here is that clk_round_rate() gives you a way to query what 
> > > > rate you would get if you were to ask for the rate to be set, without 
> > > > effecting a change in the hardware. 
> > > > 
> > > > The idea that you should call clk_round_rate() first before clk_set_rate() 
> > > > and pass the returned rounded rate into clk_set_rate() is really idiotic 
> > > > given that. Please don't do it, and please remove code which does it, and 
> > > > in review comment on it. Thanks. 
> > > 
> > > Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) 
> > > is equal to clk_round_rate(rate). So when this assumption is wrong then 
> > > it should simply be reverted. 
> > > So Liu, could you test if reverting Tomis patch fixes your problem? 
> > 
> > Yes, I'll test tomorrow when I have access to my board. 
>
> Tomi's patch cannot be reverted directly because of conflicts with the later 
> patches. So, I revert all the clock divider driver patches on top of that. 
> And, yes, after reverting Tomi's patch, I may get the correct 26.4MHz pixel 
> clock rate. 
>
> Regards, 
> Liu Ying 
>
> > 
> > Regards, 
> > Liu Ying 
> > 
> > > 
> > > Sascha 
> > > 
> > > -- 
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