Clarification needed regarding memory barrier
From: Ayyappa Ch
Date: Wed Feb 18 2015 - 10:09:23 EST
I am reading memory-barrier.txt file as mentioned below.
Please clarify my doubt .
1) For example if CPU1 got the lock , How PCI bridge can see STORE
*ADDR = 4 before STORE *DATA = 1?
ACQUIRES VS I/O ACCESSES
Under certain circumstances (especially involving NUMA), I/O accesses within
two spinlocked sections on two different CPUs may be seen as interleaved by the
PCI bridge, because the PCI bridge does not necessarily participate in the
cache-coherence protocol, and is therefore incapable of issuing the required
read memory barriers.
may be seen by the PCI bridge as follows:
STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
which would probably cause the hardware to malfunction.
Thanks and regards,
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