On Saturday 28 February 2015 08:01:11 Scott Branden wrote:OK, will change in next version.
The udelay(10) that the other drivers have seems about appropriate then,FIFO is 512 bits. I will look as to whether we can live with 1/2
and we can independently think of a way to refine the interface.
Please add a comment that explains the rate. Also, is there some kind
of FIFO present in the hwrng device? If it can store close to 1ms work
of data (1000 bits), you can just use an msleep(1) to wait for the
pool to recover.
throughput.
In that case, I think usleep_range(min(len * 8, 500), 500)) would be
a good compromise: it waits at most until the fifo is full, but might
return earlier if enough bits are available to fulfill the request.
Arnd