On Wednesday 04 March 2015 02:30 PM, Sebastian Hesselbarth wrote:[...]
On 04.03.2015 04:11, Jisheng Zhang wrote:
On Tue, 3 Mar 2015 06:56:59 -0800
Alexey Brodkin <Alexey.Brodkin@xxxxxxxxxxxx> wrote:
This allows utilization of probe deferral if master interrupt controller
was not yet probed.
In my case there's an DW APB GPIO configured as interrupt controller
which is a master for DW APB INTC.
[...]Just to get this straight for me, you are using DW_APB_INTC as a _slave_
interrupt controller of DW_APB_GPIO _master_ interrupt controller? Is
this a fictional setup to test your IP or is it a real world example?
I think Alexey is away for rest of the week so let me fill in some of the details.
The setup is indeed real and part of ARC SDP (Software Development Platform) and
these patches are precursor to getting that merged upstream.
SDP has a split main board / cpu card design, where both cards have an intc of own
to mux the irqs from respective levels. MB has a DW APB intc which sends a single
uplink to DW GPIO intc on cpu card, which in turn hooks up to ARC core. In the
final design, the board guys decided that this GPIO intc will act as a pass thru
for the downstream IRQ, but we still need to clear the interrupt on it etc - hence
it needs to properly show up in the cascaded intc hierarchy.
Does that mean if we tweak irq-dw-apb-ictlc.c enough, it could double as driver
for intc component of dw-apb-gpio too ?
+module_platform_driver(dw_apb_ictl_device_driver);This is too late. If the ictl is needed during early boot, for example
on Marvell BG2Q DMP board, we still need to calibrate the delay loop, the
kernel will hang at "Calibrating delay loop..."