Re: [PATCH 1/3] perf, x86: Add new cache events table for Haswell

[Ingo Molnar]

* Andi Kleen <andi@xxxxxxxxxxxxxx> wrote:

> From: Andi Kleen <ak@xxxxxxxxxxxxxxx>
> 
> Haswell offcore events are quite different from Sandy Bridge.
> Add a new table to handle Haswell properly.
> 
> Note that the offcore bits listed in the SDM are not quite correct
> (this is currently being fixed). An uptodate list of bits is
> in the patch.
> 
> The basic setup is similar to Sandy Bridge. The prefetch columns
> have been removed, as prefetch counting is not very reliable
> on Haswell. One L1 event that is not in the event list anymore
> has been also removed.
> 
> - data reads do not include code reads (comparable to earlier Sandy
> Bridge tables)
> - data counts include speculative execution (except L1 write, dtlb, bpu)
> - remote node access includes both remote memory, remote cache, remote mmio.
> - prefetches are not included in the counts for consistency
> (different from Sandy Bridge, which includes prefetches in the remote node)
> 
> The events with additional caveats have references to the specification update.

> +		[ C(RESULT_ACCESS) ] = 0x81d0,	/* MEM_UOPS_RETIRED.ALL_LOADS, HSM30 */
> +		[ C(RESULT_ACCESS) ] = 0x82d0,	/* MEM_UOPS_RETIRED.ALL_STORES, HSM30 */
> +		[ C(RESULT_ACCESS) ] = 0x81d0,	/* MEM_UOPS_RETIRED.ALL_LOADS, HSM30 */
> +		[ C(RESULT_ACCESS) ] = 0x82d0,	/* MEM_UOPS_RETIRED.ALL_STORES, HSM30 */

So that 'HSM30' is code for the specification update?

You'll need to properly describe HSM30 at least once instead of using 
obfuscation.

Thanks,

	Ingo
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