Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines

[Archit Taneja]

On 03/24/2015 03:40 AM, "Stéphane Viau" wrote:
> Hi Archit,
>
> > Hi Stephane,
> >
> > On 03/14/2015 01:19 AM, Stephane Viau wrote:
> > > Some interfaces (WB, DSI Command Mode) need to be kicked off
> > > through a START Signal. This signal needs to be sent at the right
> > > time and requests in some cases to keep track of the pipeline
> > > status (eg: whether pipeline registers are flushed AND output WB
> > > buffers are ready, in case of WB interface).
> > >
> > > Signed-off-by: Stephane Viau <sviau@xxxxxxxxxxxxxx>
> > > ---
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c     |   2 +
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h     |   7 +-
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c    |  31 ++--
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c     | 247
> > > ++++++++++++++++++++++++----
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h     |  72 +++-----
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  13 +-
> > >    drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h     |   1 +
> > >    7 files changed, 276 insertions(+), 97 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> > > b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> > > index c078f30..72c075a 100644
> > > --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> > > +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
> > > @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = {
> > >    	.ctl = {
> > >    		.count = 5,
> > >    		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> > > +		.flush_hw_mask = 0x0003ffff,
> > >    	},
> > >    	.pipe_vig = {
> > >    		.count = 3,
> > > @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = {
> > >    	.ctl = {
> > >    		.count = 5,
> > >    		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
> > > +		.flush_hw_mask = 0x003fffff,
> >
> > msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm
> > not wrong. Could you please add it for the next revision, or as a part
> > of the 8x16 hw cfg patch?
>
> Correct; thanks for pointing this out.
>
> IMO, this value should be 0x4003ffff because the fields are actually
> present in the register (even though the interfaces/pipes.etc. are not).
> Anyway, these bits won't be accessed because the driver won't even allow
> the usage of the corresponding resources.

Okay, that makes sense.


> I will update in the v2 of "drm/msm/mdp5: Add hardware configuration for
> msm8x16".
>
> Thanks,
> Stephane.

Thanks!
Archit

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