Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions
From: Brian Gerst
Date: Wed Apr 01 2015 - 20:32:10 EST
On Wed, Apr 1, 2015 at 6:14 PM, Linus Torvalds
> On Wed, Apr 1, 2015 at 1:52 PM, Denys Vlasenko <dvlasenk@xxxxxxxxxx> wrote:
>> BTW, AMD64 docs do explicitly say that MOVs from segment registers
>> to gpregs are zero-extending.
> Yeah, I think anything even *remotely* recent enough to do 64-bit does
> Even on the 32-bit side, anything that does register renaming is much
> better off with zero-extension than with partial register writes.
> And I found the "push" thing. It's actually documented:
> "When pushing a segment selector onto the stack, the Pentium 4,
> Intel Xeon, P6 family, and Intel486 processors
> decrement the ESP register by the operand size and then write 2 bytes.
> If the operand size is 32-bits, the upper
> two bytes of the write are not modified"
> but I can't find any similar documentation for the "mov
> Sreg->register" thing. So now I'm starting to doubt my own memory.
It's in the description of MOV:
"When the processor executes the instruction with a 32-bit
general-purpose register, it assumes that the 16 least-significant
bits of the general-purpose register are the destination or source
operand. If the register is a destination operand, the resulting
value in the two high-order bytes of the register is implementation
dependent. For the Pentium 4, Intel Xeon, and P6 family processors,
the two high-order bytes are filled with zeros; for earlier 32-bit
IA-32 processors, the two high order bytes are undefined."
AMD will always zero-extend, although this applies specifically to
"When reading segment-registers with a 32-bit operand size, the
processor zero-extends the 16-bit selector results to 32 bits. When
reading segment-registers with a 64-bit operand size, the processor
zero-extends the 16-bit selector to 64 bits."
So I think it's safe to assume zero-extension on 64-bit, but not 32-bit.
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