[PATCH v3 0/3] spi: fsl-dspi (vf610) clock fixes

From: Aaron Brice
Date: Fri Apr 03 2015 - 16:40:08 EST

We were having intermittent problems writing to SRAM chip on SPI bus on vf610
SoM. Added support for CS setup and hold times to meet the SRAM spec. In the
process noticed that the baud rate was a little high.

Changes since v2:
* Incorporate fixes per Stefen Agner review, namely moved hard-coded 50ns
delays to device tree properties
* Fix for baud rate scale value remainders, reported by Andy Shevchenko

Changes since v1:
* More detail in commit message for clock rate fix

Aaron Brice (3):
spi: fsl-dspi: Fix clock rate scale values
devicetree: spi: fsl-dspi: Add cs-sck delays
spi: fsl-dspi: Add ~50ns delay between cs and sck

.../devicetree/bindings/spi/spi-fsl-dspi.txt | 8 ++
drivers/spi/spi-fsl-dspi.c | 97 ++++++++++++++++++----
2 files changed, 89 insertions(+), 16 deletions(-)


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