Re: [PATCH 4/5] spi: img-spfi: Setup TRANSACTION register before CONTROL register

From: Andrew Bresticker
Date: Tue Apr 07 2015 - 13:59:14 EST

On Tue, Apr 7, 2015 at 4:23 AM, Mark Brown <broonie@xxxxxxxxxx> wrote:
> On Mon, Apr 06, 2015 at 02:29:06PM -0700, Andrew Bresticker wrote:
>> From: Sifan Naeem <sifan.naeem@xxxxxxxxxx>
>> Setting the transfer length in the TRANSACTION register after the
>> CONTROL register is programmed causes intermittent timeout issues in
>> SPFI transfers when using the SPI framework to control the CS GPIO
>> lines. To avoid this issue, set transfer length before programming
>> the CONTROL register.
> This is fine but it appears to be a bug fix and therefore should have
> been at the start of the series so it could be applied as such and sent
> to Linus. As it is it depends on the refactoring for prepare() which
> prevents that, please regenerate against Linus' tree so it can be sent
> as a fix.

The bug this patch fixes is only exposed once the driver is converted
to use CS GPIOs (patch 5/5 in this series), so it's not needed unless
that patch is taken. Really the entire series could be considered
fixes (with patches 2, 3, and 4 being preparatory work for patch 5)
since the switch to using CS GPIOs is to work around the hardware's
buggy CS handling. That said, support for the first SoC using this
controller (IMG Pistachio) is slated to be merged for 4.1, so I'm not
sure that pulling these fixes into 4.0 is totally necessary.

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