[PATCH] mmc: dw_mmc: add fixed divider for ciu_clk on SoCFPGA

[dinguyen]

From: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx>

The ciu_clk(Card Interface Unit Clock) on the SoCFPGA platform has a fixed
divider of 4. Add the fixed clock divide code in the platform's clock
setup code.

Technically, this code could be be moved to dw_mmc-socfpga, like the Rockchip
and Exynos, but I don't think it's necessary for a small change that is
needed for the entire SoCFPGA family of SoCs.

Also, "altr,dw-mshc-ciu-div" can be introduced to respresent the ciu divider,
but since this divider is common across all SoCFPGA, I don't think its
necessary.

Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxxxxxxxxxxxxx>
CC: Seungwon Jeon <tgih.jun@xxxxxxxxxxx>
CC: Jaehoon Chung <jh80.chung@xxxxxxxxxxx>
CC: Chris Ball <chris@xxxxxxxxxx>
CC: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
CC: Doug Anderson <dianders@xxxxxxxxxxxx>
---
 drivers/mmc/host/dw_mmc-pltfm.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..c92f790 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -26,13 +26,22 @@
 #include "dw_mmc.h"
 #include "dw_mmc-pltfm.h"
 
+#define SOCFPGA_CIU_CLK_DIV	4
+
 static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr)
 {
 	*cmdr |= SDMMC_CMD_USE_HOLD_REG;
 }
 
+static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
+{
+	host->bus_hz /= SOCFPGA_CIU_CLK_DIV;
+	return 0;
+}
+
 static const struct dw_mci_drv_data socfpga_drv_data = {
 	.prepare_command	= dw_mci_pltfm_prepare_command,
+	.setup_clock		= dw_mci_socfpga_setup_clock,
 };
 
 static const struct dw_mci_drv_data pistachio_drv_data = {
-- 
2.2.1

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