Re: [PATCH v5 2/4] arm64: dts: Add the device tree entry for the APM X-Gene PCIe MSI node

[Marc Zyngier]

On 21/04/15 05:04, Duc Dang wrote:
> There is single MSI block in X-Gene v1 SOC which serves all 5 PCIe ports.
> 
> Signed-off-by: Duc Dang <dhdang@xxxxxxx>
> Signed-off-by: Tanmay Inamdar <tinamdar@xxxxxxx>
> ---
>  arch/arm64/boot/dts/apm/apm-storm.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> index f1ad9c2..4b719c9 100644
> --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
> +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
> @@ -354,6 +354,28 @@
>  			};
>  		};
>  
> +		msi: msi@79000000 {
> +			compatible = "apm,xgene1-msi";
> +			msi-controller;
> +			reg = <0x00 0x79000000 0x0 0x900000>;

I've been repeatedly puzzled by the size of this region. In patch 1, you
say:

+ * X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where
+ * n is group number (0..F), x is index of registers in each group (0..7)
+ * The registers layout is like following:
+ * MSI0IR0                     base_addr
+ * MSI0IR1                     base_addr +  0x10000
+ * ...                         ...
+ * MSI0IR6                     base_addr +  0x60000
+ * MSI0IR7                     base_addr +  0x70000
+ * MSI1IR0                     base_addr +  0x80000
+ * MSI1IR1                     base_addr +  0x90000
+ * ...                         ...
+ * MSI1IR7                     base_addr +  0xF0000
+ * MSI2IR0                     base_addr + 0x100000
+ * ...                         ...
+ * MSIFIR0                     base_addr + 0x780000
+ * MSIFIR1                     base_addr + 0x790000
+ * ...                         ...
+ * MSIFIR7                     base_addr + 0x7F0000

which implies that the size of the region is 0x800000. Or is there
something hidden in the last 16 64k pages?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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