Re: [PATCH] perf/x86/intel/uncore: add Broadwell-U uncore IMC PMU support

[Sonny Rao]

On Wed, Apr 22, 2015 at 11:56 PM, Stephane Eranian <eranian@xxxxxxxxxx> wrote:
>
> This patch enables the uncore Memory Controller (IMC) PMU support
> for Intel Broadwell-U (Model 61) mobile processors.
> The IMC PMU enables measuring memory bandwidth.
>
> To use with perf:
> $ perf stat -a -I 1000 -e uncore_imc/data_reads/,uncore_imc/data_writes/ sleep 10
>
> Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>

Tested-by: Sonny Rao <sonnyrao@xxxxxxxxxxxx>

> ---
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> index c635b8b..a03f964 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
> @@ -922,6 +922,9 @@ static int __init uncore_pci_init(void)
>         case 69: /* Haswell Celeron */
>                 ret = hsw_uncore_pci_init();
>                 break;
> +       case 61: /* Broadwell */
> +               ret = bdw_uncore_pci_init();
> +               break;
>         default:
>                 return 0;
>         }
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> index 6c8c1e7..06b0793 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
> @@ -326,6 +326,7 @@ extern struct event_constraint uncore_constraint_empty;
>  int snb_uncore_pci_init(void);
>  int ivb_uncore_pci_init(void);
>  int hsw_uncore_pci_init(void);
> +int bdw_uncore_pci_init(void);
>  void snb_uncore_cpu_init(void);
>  void nhm_uncore_cpu_init(void);
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
> index 0333d0b..0f768bf 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
> @@ -7,6 +7,7 @@
>  #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
>  #define PCI_DEVICE_ID_INTEL_HSW_IMC    0x0c00
>  #define PCI_DEVICE_ID_INTEL_HSW_U_IMC  0x0a04
> +#define PCI_DEVICE_ID_INTEL_BDW_IMC    0x1604
>
>  /* SNB event control */
>  #define SNB_UNC_CTL_EV_SEL_MASK                        0x000000ff
> @@ -488,6 +489,14 @@ static const struct pci_device_id hsw_uncore_pci_ids[] = {
>         { /* end: all zeroes */ },
>  };
>
> +static const struct pci_device_id bdw_uncore_pci_ids[] = {
> +       { /* IMC */
> +               PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC),
> +               .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
> +       },
> +       { /* end: all zeroes */ },
> +};
> +
>  static struct pci_driver snb_uncore_pci_driver = {
>         .name           = "snb_uncore",
>         .id_table       = snb_uncore_pci_ids,
> @@ -503,6 +512,11 @@ static struct pci_driver hsw_uncore_pci_driver = {
>         .id_table       = hsw_uncore_pci_ids,
>  };
>
> +static struct pci_driver bdw_uncore_pci_driver = {
> +       .name           = "bdw_uncore",
> +       .id_table       = bdw_uncore_pci_ids,
> +};
> +
>  struct imc_uncore_pci_dev {
>         __u32 pci_id;
>         struct pci_driver *driver;
> @@ -516,6 +530,7 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
>         IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
>         IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */
>         IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */
> +       IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver),    /* 5th Gen Core U */
>         {  /* end marker */ }
>  };
>
> @@ -563,6 +578,11 @@ int hsw_uncore_pci_init(void)
>         return imc_uncore_pci_init();
>  }
>
> +int bdw_uncore_pci_init(void)
> +{
> +       return imc_uncore_pci_init();
> +}
> +
>  /* end of Sandy Bridge uncore support */
>
>  /* Nehalem uncore support */
> --
> 2.1.0
>
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