Re: [RFC] Design for flag bit outputs from asms

[Richard Henderson]

On 05/04/2015 01:45 PM, Linus Torvalds wrote:
> On Mon, May 4, 2015 at 1:33 PM, Richard Henderson <rth@xxxxxxxxxx> wrote:
>>
>> A fair point.  Though honestly, I was hoping that this feature would mostly be
>> used for conditions that are "weird" -- that is, not normally describable by
>> arithmetic at all.  Otherwise, why are you using inline asm for it?
> 
> I could easily imagine using some of the combinations for atomic operations.
> 
> For example, doing a "lock decl", and wanting to see if the result is
> negative or zero. Sure, it would be possible to set *two* booleans (ZF
> and SF), but there's a contiional for "BE"..

Sure.

I'd be more inclined to support these compound conditionals directly, rather
than try to get the compiler to recognize them after the fact.

Indeed, I believe we have a near complete set of them in the x86 backend
already.  It'd just be a matter of selecting the spellings for the constraints.


r~
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