Re: [PATCH v4 02/20] clk: tegra: periph: add new periph clks and muxes for Tegra210

[Thierry Reding]

On Mon, May 04, 2015 at 12:37:22PM -0400, Rhyland Klein wrote:
[...]
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
[...]
> @@ -387,6 +563,32 @@ static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = {
>  	[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7,
>  };
>  
> +/* SOR1 mux'es */
> +static const char *mux_pllp_plld_plld2_clkm[] = {
> +	"pll_p", "pll_d_out0", "pll_d2", "clk_m"
> +};

I think "pll_d2" above needs to be "pll_d2_out0". Otherwise we're not
going to be able to make HDMI work.

> +static u32 mux_pllp_plld_plld2_clkm_idx[] = {
> +	[0] = 0, [1] = 2, [2] = 5, [3] = 6
> +};

I also think the below...

> +static const char *mux_plldp_sor1_src[] = {
> +	"pll_dp", "clk_sor1_src"
> +};
> +#define mux_plldp_sor1_src_idx NULL
> +
> +static const char *mux_clkm_sor1_brick_sor1_src[] = {
> +	"clk_m", "sor1_brick", "sor1_src", "sor1_brick"
> +};
> +#define mux_clkm_sor1_brick_sor1_src_idx NULL

... aren't going to cut it. The problem is that we now have a three
level hierarchy, which makes it very cumbersome to set the correct
parent from the display driver. I have a local patch that implements
this by adding a new type of mux which works on a mask rather than a
single bitfield so that we can represent the various parents of the
SOR1 clock in a single level.

I think for now we can leave this in place and apply my patch on top
after everybody agrees it's the right thing to do.

Thierry

Attachment: pgpkgqYXpKYcw.pgp
Description: PGP signature