Re: [PATCH] ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)

From: Thomas . Betker
Date: Tue May 12 2015 - 08:42:21 EST

> >> This patch is based on the
> >> commit 1a8e41cd672f ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
> >> (cache controller) AuxCtlr register")
> >
> >
> > I've been under the impression that this shouldn't be done in the
> > kernel, but in the boot loader/firmware:
> >
> >
> >
> >
> Tegra, Exynos, sti still have this bit set.

In 4.1-rc3, the bit is set by berlin, exynos, nomadik, omap2, sti, tegra,

> Does that mean that they should be just removed because fix should be in
> bootloader?
> Anyway it is normal that bootloader stay on system untouched and only OS
> is updated. But OK - let's make this in bootloader if this is preferred
> solution.

So the plan is to update each and every Zynq bootloader for a problem we
have encountered in Linux (in our case, a problem we have been hunting for
months)? My u-boot doesn't even use the cache; it's disabled until the
kernel boots.

I do understand that the kernel should not overwrite hardwired settings
such as cache size, but shouldn't we at least allow to fix things that
definitely need to be fixed?

Best regards,
Thomas Betker
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