Re: Mwait usage on AMD processors

[Borislav Petkov]

On Thu, May 14, 2015 at 09:38:57PM +0800, Huang Rui wrote:
> Is C1E here you mentioned is waiting state that use mwaitx enters at
> AMD platform? If yes, please see below comments:
> 
> Current processor:
> Power saving: C0 < C1E (AMD) < C1

How is C1 > C1E ?

C1E is the Enhanced C1.

> Performance: Halt < Mwait <= Mwaitx

What performance? You're idle.

> Halt -> C1, and Mwaitx/Mwait -> C1E (AMD)

Huh? Right now we do HLT on all AMD and the hw enters C1E after a bunch
of stuff is fulfilled first. Are the plans to enter C1E from MWAIT now?

> Consider about the balance between power consumption and performance,
> so we want to expose the interface. And mwaitx has different opcode
> with traditional mwait.

There's alternative()'s for that.

> Due to C1E (AMD) less power saving that real C1, so you can think it
> still in C0 at current.

Which CPUs, current or upcoming?

If you want to do MWAITX for upcoming CPUs, simply define your own idle
routine and select it in select_idle_routine().

> In furture processor:
> HW designer would do Mwaitx -> C1 or deeper low power state.
> 
> BTW, could I expose it and send the patches to review?

You can always send out the patches, sure.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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