Re: [PATCH v5 21/21] clk: tegra: pll: Fix issues with rates for VCO PLLs

[Benson Leung]

On Tue, May 12, 2015 at 10:24 AM, Rhyland Klein <rklein@xxxxxxxxxx> wrote:
> From: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
>
> Without this change clk_get_rate would return the final output
> rather than the VCO output as it would factor in the pdiv when
> it shouldn't. This will cause problems for all dividers in the
> subtree of the VCO PLL.
>
> Signed-off-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Signed-off-by: Rhyland Klein <rklein@xxxxxxxxxx>

Reviewed-by: Benson Leung <bleung@xxxxxxxxxxxx>

-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@xxxxxxxxxxxx
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