Re: [PATCH v2 02/11] perf/x86: Improve HT workaround GP counter constraint

[Peter Zijlstra]

Please trim your email.

On Tue, May 26, 2015 at 02:37:52AM -0700, Stephane Eranian wrote:
> > @@ -822,8 +830,24 @@ int x86_schedule_events(struct cpu_hw_ev
> >
> >         /* slow path */
> >         if (i != n) {
> > +               int gpmax = x86_pmu.num_counters;
> > +
> > +               /*
> > +                * Do not allow scheduling of more than half the available
> > +                * generic counters.
> > +                *
> > +                * This helps avoid counter starvation of sibling thread by
> > +                * ensuring at most half the counters cannot be in exclusive
> > +                * mode. There is no designated counters for the limits. Any
> > +                * N/2 counters can be used. This helps with events with
> > +                * specific counter constraints.
> > +                */
> > +               if (is_ht_workaround_enabled() && !cpuc->is_fake &&
> > +                   READ_ONCE(cpuc->excl_cntrs->exclusive_present))
> > +                       gpmax /= 2;
> > +
> What I don't like about this part is that this is a hack to work around a bug
> on some limited Intel CPUs and yet it is in the middle of generic x86 code.
> I understand it will be inoperative on AMD PMU and is not used by Intel
> uncore. On KNC or P6, you will not have is_ht_workaround_enabled().
> Could this be made a x86_pmu callback? x86_pmu.counter_limit()?

It'll be slower though. You get an indirect function call in there.

But sure we can clean that up later if you like; there's other things
needing to be fixed here first.

I'm going to overhaul the whole get/put constraints stuff first.
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