Re: [PATCH 0/3] MIPS: SMP memory barriers: lightweight sync, acquire-release

[Ralf Baechle]

On Tue, Jun 02, 2015 at 02:59:38PM -0400, Joshua Kinard wrote:

> >> How useful might this be for older hardware, such as the R10k CPUs?  Just
> >> fallbacks to the old sync insn?
> > 
> > The R10000 family is strongly ordered so there is no SYNC instruction
> > required in the entire kernel even though some Origin hardware documentation
> > incorrectly claims otherwise.
> 
> So no benefits even in the speculative execution case on noncoherent hardware
> like IP28 and IP32?

That's handled entirely differently by using a CACHE BARRIER instruction,
something which is specific to the R10000-family.  It's also used
differently by putting once such instruction at the end of every basic
block that might result in speculatively dirty cache lines.

Note that these systems affected by this speculation issue are all
non-coherent uniprocessor systems while Leonid's patch matters for
SMP kernels; the primitives he's changed will not genrate any code for
a !CONFIG_SMP kernel.

  Ralf
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