Re: [PATCH v5 14/21] clk: tegra: pll: Adjust vco_min if SDM present

[Stephen Boyd]

On 05/12, Rhyland Klein wrote:
> From: Bill Huang <bilhuang@xxxxxxxxxx>
> 
> This code makes use of the SDM fractional divider if present to
> contrain the allowable programming range of the PLL divider register

s/contrain/constrain/

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