Re: [PATCH 3/3] clk: pistachio: Add sanity checks on PLL configuration

From: Stephen Boyd
Date: Thu Jun 04 2015 - 15:48:52 EST


On 05/26, Ezequiel Garcia wrote:
> From: Kevin Cernekee <cernekee@xxxxxxxxxxxx>
>
> When setting the PLL rates, check that:
>
> - VCO is within range
> - PFD is within range
> - PLL is disabled when postdiv is changed
> - postdiv2 <= postdiv1
>
> Reviewed-by: Andrew Bresticker <abrestic@xxxxxxxxxxxx>
> Signed-off-by: Kevin Cernekee <cernekee@xxxxxxxxxxxx>
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@xxxxxxxxxx>
> ---

Applied to clk-next

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