From 7fc64b43b214ab3b39504a86a3561cc6b70c9555 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Fri, 12 Jun 2015 14:51:02 +0200 Subject: [PATCH] crypto: caam: use generic *_relaxed io functions In preparation for supporting ARM architectures this removes much of the various defines for the different architecture combinations by relying on the arch specific definitions. The two ommissions are the PPC specific bits that need to be added and the 64-bit readq/writeq implementations. Note this change reverts commit ef94b1d834aace7101de77c3a7c2631b9ae9c5f6 as that change does not work for ARM little endian systems. --- drivers/crypto/caam/ctrl.c | 46 ++++++++++++++++++------------------- drivers/crypto/caam/jr.c | 34 ++++++++++++++-------------- drivers/crypto/caam/regs.h | 56 +++++++++++++++------------------------------- 3 files changed, 58 insertions(+), 78 deletions(-) diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index efba4cc..dddce65 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -90,7 +90,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, if (ctrlpriv->virt_en == 1) { setbits32(&ctrl->deco_rsr, DECORSR_JR0); - while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && + while (!(readl_relaxed(&ctrl->deco_rsr) & DECORSR_VALID) && --timeout) cpu_relax(); @@ -99,7 +99,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); - while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && + while (!(readl_relaxed(&ctrl->deco_rq) & DECORR_DEN0) && --timeout) cpu_relax(); @@ -110,7 +110,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, } for (i = 0; i < desc_len(desc); i++) - wr_reg32(&deco->descbuf[i], *(desc + i)); + writel_relaxed(*(desc + i), &deco->descbuf[i]); flags = DECO_JQCR_WHL; /* @@ -121,11 +121,11 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, flags |= DECO_JQCR_FOUR; /* Instruct the DECO to execute it */ - wr_reg32(&deco->jr_ctl_hi, flags); + writel_relaxed(flags, &deco->jr_ctl_hi); timeout = 10000000; do { - deco_dbg_reg = rd_reg32(&deco->desc_dbg); + deco_dbg_reg = readl_relaxed(&deco->desc_dbg); /* * If an error occured in the descriptor, then * the DECO status field will be set to 0x0D @@ -136,7 +136,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, cpu_relax(); } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); - *status = rd_reg32(&deco->op_status_hi) & + *status = readl_relaxed(&deco->op_status_hi) & DECO_OP_STATUS_HI_ERR_MASK; if (ctrlpriv->virt_en == 1) @@ -206,7 +206,7 @@ static int instantiate_rng(struct device *ctrldev, int state_handle_mask, * without any error (HW optimizations for later * CAAM eras), then try again. */ - rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; + rdsta_val = readl_relaxed(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; if (status || !(rdsta_val & (1 << sh_idx))) ret = -EAGAIN; if (ret) @@ -334,7 +334,7 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) * time trying to set the values controlling the sample * frequency, the function simply returns. */ - val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) + val = (readl_relaxed(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) >> RTSDCTL_ENT_DLY_SHIFT; if (ent_delay <= val) { /* put RNG4 into run mode */ @@ -342,16 +342,16 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) return; } - val = rd_reg32(&r4tst->rtsdctl); + val = readl_relaxed(&r4tst->rtsdctl); val = (val & ~RTSDCTL_ENT_DLY_MASK) | (ent_delay << RTSDCTL_ENT_DLY_SHIFT); - wr_reg32(&r4tst->rtsdctl, val); + writel_relaxed(val, &r4tst->rtsdctl); /* min. freq. count, equal to 1/4 of the entropy sample length */ - wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); + writel_relaxed(ent_delay >> 2, &r4tst->rtfrqmin); /* disable maximum frequency count */ - wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); + writel_relaxed(RTFRQMAX_DISABLE, &r4tst->rtfrqmax); /* read the control register */ - val = rd_reg32(&r4tst->rtmctl); + val = readl_relaxed(&r4tst->rtmctl); /* * select raw sampling in both entropy shifter * and statistical checker @@ -360,7 +360,7 @@ static void kick_trng(struct platform_device *pdev, int ent_delay) /* put RNG4 into run mode */ clrbits32(&val, RTMCTL_PRGM); /* write back the control register */ - wr_reg32(&r4tst->rtmctl, val); + writel_relaxed(val, &r4tst->rtmctl); } /** @@ -416,7 +416,7 @@ static int caam_probe(struct platform_device *pdev) return -ENOMEM; } /* Finding the page size for using the CTPR_MS register */ - comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); + comp_params = readl_relaxed(&ctrl->perfmon.comp_parms_ms); pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; /* Allocating the BLOCK_OFFSET based on the supported page size on @@ -451,7 +451,7 @@ static int caam_probe(struct platform_device *pdev) * Read the Compile Time paramters and SCFGR to determine * if Virtualization is enabled for this platform */ - scfgr = rd_reg32(&ctrl->scfgr); + scfgr = readl_relaxed(&ctrl->scfgr); ctrlpriv->virt_en = 0; if (comp_params & CTPR_MS_VIRT_EN_INCL) { @@ -523,7 +523,7 @@ static int caam_probe(struct platform_device *pdev) /* Check to see if QI present. If so, enable */ ctrlpriv->qi_present = - !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & + !!(readl_relaxed(&ctrl->perfmon.comp_parms_ms) & CTPR_MS_QI_MASK); if (ctrlpriv->qi_present) { ctrlpriv->qi = (struct caam_queue_if __force *) @@ -531,7 +531,7 @@ static int caam_probe(struct platform_device *pdev) BLOCK_OFFSET * QI_BLOCK_NUMBER ); /* This is all that's required to physically enable QI */ - wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); + writel_relaxed(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo); } /* If no QI and no rings specified, quit and go home */ @@ -541,7 +541,7 @@ static int caam_probe(struct platform_device *pdev) return -ENOMEM; } - cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); + cha_vid_ls = readl_relaxed(&ctrl->perfmon.cha_id_ls); /* * If SEC has RNG version >= 4 and RNG state handle has not been @@ -549,7 +549,7 @@ static int caam_probe(struct platform_device *pdev) */ if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { ctrlpriv->rng4_sh_init = - rd_reg32(&ctrl->r4tst[0].rdsta); + readl_relaxed(&ctrl->r4tst[0].rdsta); /* * If the secure keys (TDKEK, JDKEK, TDSK), were already * generated, signal this to the function that is instantiating @@ -560,7 +560,7 @@ static int caam_probe(struct platform_device *pdev) ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; do { int inst_handles = - rd_reg32(&ctrl->r4tst[0].rdsta) & + readl_relaxed(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; /* * If either SH were instantiated by somebody else @@ -610,8 +610,8 @@ static int caam_probe(struct platform_device *pdev) /* NOTE: RTIC detection ought to go here, around Si time */ - caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | - (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); + caam_id = (u64)readl_relaxed(&ctrl->perfmon.caam_id_ms) << 32 | + readl_relaxed(&ctrl->perfmon.caam_id_ls); /* Report "alive" for developer to see */ dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index b8b5d47..ae1ddc2 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -34,12 +34,12 @@ static int caam_reset_hw_jr(struct device *dev) setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); /* initiate flush (required prior to reset) */ - wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); - while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == + writel_relaxed(JRCR_RESET, &jrp->rregs->jrcommand); + while (((readl_relaxed(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == JRINT_ERR_HALT_INPROGRESS) && --timeout) cpu_relax(); - if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) != + if ((readl_relaxed(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) != JRINT_ERR_HALT_COMPLETE || timeout == 0) { dev_err(dev, "failed to flush job ring %d\n", jrp->ridx); return -EIO; @@ -47,8 +47,8 @@ static int caam_reset_hw_jr(struct device *dev) /* initiate reset */ timeout = 100000; - wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); - while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) + writel_relaxed(JRCR_RESET, &jrp->rregs->jrcommand); + while ((readl_relaxed(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) cpu_relax(); if (timeout == 0) { @@ -79,8 +79,8 @@ int caam_jr_shutdown(struct device *dev) free_irq(jrp->irq, dev); /* Free rings */ - inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); - outbusaddr = rd_reg64(&jrp->rregs->outring_base); + inpbusaddr = readq_relaxed(&jrp->rregs->inpring_base); + outbusaddr = readq_relaxed(&jrp->rregs->outring_base); dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH, jrp->inpring, inpbusaddr); dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH, @@ -132,7 +132,7 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) * Check the output ring for ready responses, kick * tasklet if jobs done. */ - irqstate = rd_reg32(&jrp->rregs->jrintstatus); + irqstate = readl_relaxed(&jrp->rregs->jrintstatus); if (!irqstate) return IRQ_NONE; @@ -150,7 +150,7 @@ static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); /* Have valid interrupt at this point, just ACK and trigger */ - wr_reg32(&jrp->rregs->jrintstatus, irqstate); + writel_relaxed(irqstate, &jrp->rregs->jrintstatus); preempt_disable(); tasklet_schedule(&jrp->irqtask); @@ -169,7 +169,7 @@ static void caam_jr_dequeue(unsigned long devarg) u32 *userdesc, userstatus; void *userarg; - while (rd_reg32(&jrp->rregs->outring_used)) { + while (readl_relaxed(&jrp->rregs->outring_used)) { head = ACCESS_ONCE(jrp->head); @@ -203,7 +203,7 @@ static void caam_jr_dequeue(unsigned long devarg) userstatus = jrp->outring[hw_idx].jrstatus; /* set done */ - wr_reg32(&jrp->rregs->outring_rmvd, 1); + writel_relaxed(1, &jrp->rregs->outring_rmvd); jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) & (JOBR_DEPTH - 1); @@ -335,7 +335,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, head = jrp->head; tail = ACCESS_ONCE(jrp->tail); - if (!rd_reg32(&jrp->rregs->inpring_avail) || + if (!readl_relaxed(&jrp->rregs->inpring_avail) || CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) { spin_unlock_bh(&jrp->inplock); dma_unmap_single(dev, desc_dma, desc_size, DMA_TO_DEVICE); @@ -357,7 +357,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, (JOBR_DEPTH - 1); jrp->head = (head + 1) & (JOBR_DEPTH - 1); - wr_reg32(&jrp->rregs->inpring_jobadd, 1); + writel_relaxed(1, &jrp->rregs->inpring_jobadd); spin_unlock_bh(&jrp->inplock); @@ -416,10 +416,10 @@ static int caam_jr_init(struct device *dev) jrp->head = 0; jrp->tail = 0; - wr_reg64(&jrp->rregs->inpring_base, inpbusaddr); - wr_reg64(&jrp->rregs->outring_base, outbusaddr); - wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); - wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); + writeq_relaxed(inpbusaddr, &jrp->rregs->inpring_base); + writeq_relaxed(outbusaddr, &jrp->rregs->outring_base); + writel_relaxed(JOBR_DEPTH, &jrp->rregs->inpring_size); + writel_relaxed(JOBR_DEPTH, &jrp->rregs->outring_size); jrp->ringsize = JOBR_DEPTH; diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index 378ddc1..0f7d3b8 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -65,52 +65,32 @@ * */ -#ifdef __BIG_ENDIAN -#define wr_reg32(reg, data) out_be32(reg, data) -#define rd_reg32(reg) in_be32(reg) -#ifdef CONFIG_64BIT -#define wr_reg64(reg, data) out_be64(reg, data) -#define rd_reg64(reg) in_be64(reg) -#endif +#ifndef CONFIG_64BIT +#if defined(__BIG_ENDIAN) || defined (CONFIG_ARM) +#define REG64_HI32(reg) ((u32 __iomem *)(reg)) +#define REG64_LO32(reg) ((u32 __iomem *)(reg) + 1) #else -#ifdef __LITTLE_ENDIAN -#define wr_reg32(reg, data) __raw_writel(data, reg) -#define rd_reg32(reg) __raw_readl(reg) -#ifdef CONFIG_64BIT -#define wr_reg64(reg, data) __raw_writeq(data, reg) -#define rd_reg64(reg) __raw_readq(reg) -#endif -#endif +#define REG64_HI32(reg) ((u32 __iomem *)(reg) + 1) +#define REG64_LO32(reg) ((u32 __iomem *)(reg)) #endif -#ifndef CONFIG_64BIT -#ifdef __BIG_ENDIAN -static inline void wr_reg64(u64 __iomem *reg, u64 data) -{ - wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); - wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull); -} - -static inline u64 rd_reg64(u64 __iomem *reg) +static inline void writeq(u64 data, u64 __iomem *reg) { - return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) | - ((u64)rd_reg32((u32 __iomem *)reg + 1)); + writel_relaxed(data >> 32, REG64_HI32(reg)); + writel_relaxed(data, REG64_LO32(reg)); } -#else -#ifdef __LITTLE_ENDIAN -static inline void wr_reg64(u64 __iomem *reg, u64 data) + +static inline u64 readq(u64 __iomem *reg) { - wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32); - wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull); + return ((u64)readl_relaxed(REG64_HI32(reg))) << 32 | + readl_relaxed(REG64_LO32(reg)); } - -static inline u64 rd_reg64(u64 __iomem *reg) -{ - return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) | - ((u64)rd_reg32((u32 __iomem *)reg)); -} -#endif #endif + +/* These are common macros for Power add them if they aren't defined*/ +#ifndef CONFIG_PPC +#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) +#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) #endif /* -- 1.8.3.1