Re: [Intel-gfx] [PATCH] drm/i915: Clear pipe's pll hw state in hsw_dp_set_ddi_pll_sel()

[Daniel Vetter]

On Tue, Jun 30, 2015 at 04:47:06PM +0300, Jani Nikula wrote:
> On Tue, 30 Jun 2015, Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx> wrote:
> > Similarly to what is done for SKL, clear the dpll_hw_state of the pipe
> > config in hsw_dp_set_ddi_pll_sel(), since it main contain stale values.
> > That can happen if a crtc that was previously driving an HDMI connector
> > switches to a DP connector. In that case, the wrpll field was left with
> > its old value, leading to warnings like the one below:
> >
> > [drm:check_crtc_state [i915]] *ERROR* mismatch in dpll_hw_state.wrpll (expected 0xb035061f, found 0x00000000)
> > ------------[ cut here ]------------
> > WARNING: CPU: 1 PID: 767 at drivers/gpu/drm/i915/intel_display.c:12324 check_crtc_state+0x975/0x10b0 [i915]()
> > pipe state doesn't match!
> >
> > This regression was indroduced in
> >
> > commit dd3cd74acf12723045a64f1f2c6298ac7b34a5d5
> > Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
> > Date:   Fri May 15 13:34:29 2015 +0300
> >
> >     drm/i915: Don't overwrite (e)DP PLL selection on SKL
> >
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
> 
> Reported-by: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
> Tested-by: Jani Nikula <jani.nikula@xxxxxxxxx>

Yeah makes sense as a fix for 4.2. But for 4.3 I wonder whether the
original commit that started this chain needs to be changed a bit:

commit 4978cc93d9ac240b435ce60431aef24239b4c270
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx>
Date:   Tue Apr 21 17:13:21 2015 +0300

    drm/i915: Preserve shared DPLL information in new pipe_config

All the trouble this caused is because it not only preserves the sharing
config (in crtc_state->shared_dpll) but also the ->dpll_hw_state. And I
think with Maarten's latest code (for 4.3) we'd just do an unconditional
compute_config (need it for fast pfit updates and fastboot), which means
the bogus values in ->dpll_hw_state aren't a problem any more since we'll
overwrite them again. And then we could remove that sprinkle of memsets we
have all over, which would be good (since the current approach is
obviously a bit fragile). Anyway:

Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>

Thanks, Daniel

> 
> > ---
> >
> > Only compile tested, for the wrpll warning.
> >
> > Thanks,
> > Ander
> >
> >  drivers/gpu/drm/i915/intel_dp.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 4ebfc3a..fbd9ac3 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1147,6 +1147,9 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
> >  static void
> >  hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
> >  {
> > +	memset(&pipe_config->dpll_hw_state, 0,
> > +	       sizeof(pipe_config->dpll_hw_state));
> > +
> >  	switch (link_bw) {
> >  	case DP_LINK_BW_1_62:
> >  		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
> > -- 
> > 2.1.0
> >
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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