Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface

[Thomas Gleixner]

On Mon, 6 Jul 2015, Ingo Molnar wrote:
 
> * Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> wrote:
> 
> > The patch adds CHT PMC interface. This exposes all the South IP device power
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > not aligned. This is fixed by splitting a common mapping on per register basis.
> > 
> > Signed-off-by: Kumar P Mahesh <mahesh.kumar.p@xxxxxxxxx>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> 
> That's a weird signoff sequence. I changed it to:
> 
>  Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
>  Acked-by: Kumar P Mahesh <mahesh.kumar.p@xxxxxxxxx>

It might lack a From: Kumar ... 
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