Re: [PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected

[Andy Shevchenko]

On Wed, 2015-06-17 at 22:03 +0300, Andy Shevchenko wrote:
> On Intel Edison we have a nice implementation of x86 platform without 
> legacy
> PIC and with specific PCI. There are devices which are not using 
> interrupt by
> some reasons, but have them as IRQ0 in the PCI configuration. 
> Suprisingly the
> first eMMC host controller is the actual user for IRQ0. Since we have 
> serial
> driver implemented that enumerates unused serial IP (one of four) 
> which has
> IRQ0 assigned we, in case it gets it first by pci_enable_device(), 
> lost a
> possibility to probe eMMC. 

Any comments on that?

> 
> So, this series provides a workaround (patch 2) and small fix of 
> error code
> (patch 1).
> 
> I wonder if this can go to v4.2. What do you think?
> 
> Andy Shevchenko (2):
>   x86: intel_mid_pci: propagate actual return code
>   x86: intel_mid_pci: work around for IRQ0 assignment
> 
>  arch/x86/pci/intel_mid_pci.c | 27 ++++++++++++++++++++++++---
>  1 file changed, 24 insertions(+), 3 deletions(-)
> 

-- 
Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
Intel Finland Oy
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