RE: Re: [V2 PATCH 1/3] x86/panic: Fix re-entrance problem due to panic on NMI

[æåèå / KAWAIïHIDEHIRO]

Hi,

> -----Original Message-----
> From: Michal Hocko [mailto:mhocko@xxxxxxxxxx]
> 
> On Thu 30-07-15 07:33:15, æåèå / KAWAIïHIDEHIRO wrote:
> [...]
> > Are you using SGI UV?  On that platform, NMIs may be delivered to
> > all cpus because LVT1 of all cpus are not masked as follows:
> 
> This is Compute Blade 520XB1 from Hitachi with 240 cpus.

Thanks for the information!

I asked my colleague in other department about NMI button behavior
of our server just before receive your mail, and certainly what you
said happens; all cpus say "Uhhuh. NMI received for unknown reason 3d
on CPU N" when NMI button is pusshed.  So, this was also our problem...

N‹§²æ¸›yú²X¬¶ÇvØ–)Þ{.nlj·¥Š{±‘êX§¶›¡Ü}©ž²ÆzÚj:+v‰¨¾«‘êZ+€Êzf£¢·hšˆ§~†­†Ûÿû®w¥¢¸?™¨è&¢)ßf”ùy§m…á«a¶Úÿ0¶ìå