Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

[Thomas Gleixner]

On Fri, 31 Jul 2015, Shaohua Li wrote:
> @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
>  	apic_write(APIC_LVTT, lvtt_value);
>  
>  	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
> +		u64 msr;
> +
> +		/*
> +		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
> +		 * writing APIC LVTT and TSC_DEADLINE MSR isn't serialized.
> +		 * This uses the algorithm described in Intel SDM to serialize
> +		 * the two writes
> +		 * */
> +		while (1) {
> +			wrmsrl(MSR_IA32_TSC_DEADLINE, -1L);
> +			rdmsrl(MSR_IA32_TSC_DEADLINE, msr);
> +			if (msr)
> +				break;
> +		}
> +		wrmsrl(MSR_IA32_TSC_DEADLINE, 0);


I think this is exceptionally silly. A proper fence after the
apic_write() should have the same effect.

Thanks,

	tglx
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