[PATCH 0/3] Add eFuse driver of Rockchip SoC

[Shunqian Zheng]

From: ZhengShunQian <zhengsq@xxxxxxxxxxxxxx>

Base on nvmem framework, this three patches
implement the eFuse driver of Rockchip SoC.
The data from eFuse contains CPU leakage, chip code and version etc.

The flow of reading data from eFuse is quite simple,
config the CTRL register, write data address to CTRL
register, then data is available in DOUT register.

Although always enable eFuse clock seems awkward,
I can't find a better method to enable clock before
read/write in the nvmem framework.
Appreciate for any suggestions.


ZhengShunQian (3):
  nvmem: fix the out-of-range leak in read/write()
  nvmem: rockchip-efuse: implement eFuse driver
  clk: rockchip: do not gate the efuse256 clock

 .../devicetree/bindings/nvmem/rockchip-efuse.txt   |  36 +++++
 arch/arm/boot/dts/rk3288.dtsi                      |  13 ++
 drivers/clk/rockchip/clk-rk3288.c                  |   2 +-
 drivers/nvmem/Kconfig                              |  10 ++
 drivers/nvmem/Makefile                             |   2 +
 drivers/nvmem/core.c                               |   4 +-
 drivers/nvmem/rockchip-efuse.c                     | 155 +++++++++++++++++++++
 include/dt-bindings/clock/rk3288-cru.h             |   1 +
 8 files changed, 220 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
 create mode 100644 drivers/nvmem/rockchip-efuse.c

-- 
1.9.1

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