Re: [4.1,013/123] MIPS: c-r4k: Fix cache flushing for MT cores

From: Leonid Yegoshin
Date: Mon Aug 10 2015 - 14:36:48 EST

On 08/08/2015 03:08 PM, gregkh@xxxxxxxxxxxxxxxxxxx wrote:
4.1-stable review patch. If anyone has any objections, please let me know.

Yes, I have objection. Please look into excepts from my mail exchange with Markos:

On 06/25/2015 03:59 AM, Markos Chandras wrote:

@@ -51,9 +51,8 @@ static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
- smp_call_function(func, info, 1);
+ if (config_enabled(CONFIG_SMP))
+ smp_call_function_many(&cpu_foreign_map, func, info, 1);

You can NOT do this because r4k_on_each_cpu() is still used for non-MIPS/IMG processors for SAFE INDEX cache flushes - cpu_has_safe_index_cacheops (it is not safe in CM/CM2/CM3 environment).

And a little explanation and history:

The function r4k_on_each_cpu() can NOT be used simultaneously for index cacheops and address cacheops because both have a different rules in applying in other cores and that is different in inter-core HW blocks of various vendors. CM propogates address cacheops from core-to-core (no IPI calls are needed) but another vendors may do not - this is indicated by CONFIG_MIPS_MT_SMP (and a dropped now CONFIG_MIPS_MT_SMTC).

Unfortunately, before this function was used for index cacheops too in any kernel and that is WRONG, at least for CM-based systems.
So, I splitted index and address cacheops and wrote a functions r4k_indexop_on_each_cpu and put it in use in at least in dlm- and it finally made a way to dev-linux-mti-3.6. This is a famous patch named:

MIPS: Cache flush functions are reworked.

This patch is a preparation for EVA support in kernel.

However, it also fixes a bug then index cacheop was not ran
on multiple CPUs with unsafe index cacheops (flush_cache_vmap,
flush_icache_range, flush_cache_range, __flush_cache_all).

Additionally, it optimizes a usage of index and address cacheops for
address range flushes depending from address range size.

Because of that reasons it is a separate patch from EVA support.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@xxxxxxxxxx>
Signed-off-by: Steven J. Hill <Steven.Hill@xxxxxxxxxx>
(cherry picked from commit 6b05dd71da1136fbad0ce642790c4c99343f05e7)

(history is skipped)

Note: the replacement of

if (config_enabled(CONFIG_SMP))

if (!mips_cm_present())

doesn't solve a problem - in CM-based environment the index cache ops MUST be delivered to other core via IPI.

- Leonid.

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