Re: [PATCH v1 1/5] clk: rockchip: rk3288: Add the clock id of eFuse

[Shunqian Zheng]

Heiko,

On 2015å08æ11æ 15:22, Heiko StÃbner wrote:
> Am Dienstag, 11. August 2015, 09:16:32 schrieb Heiko StÃbner:
> > Am Dienstag, 11. August 2015, 14:15:02 schrieb Shunqian Zheng:
> > > From: ZhengShunQian <zhengsq@xxxxxxxxxxxxxx>
> > >
> > > The clock id is necessary item, changing it from 0
> > > then can be referred in driver and device tree.
> > >
> > > Signed-off-by: ZhengShunQian <zhengsq@xxxxxxxxxxxxxx>
> > Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx>
> >
> >
> > Patch is missing the clock maintainers and list
> > Mike Turquette <mturquette@xxxxxxxxxxxx>
> > Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> > linux-clk@xxxxxxxxxxxxxxx
I will re-send this patch and cc to clock maintainers later...
> > > ---
> > >
> > >   drivers/clk/rockchip/clk-rk3288.c      | 2 +-
> > >   include/dt-bindings/clock/rk3288-cru.h | 1 +
> > >   2 files changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/rockchip/clk-rk3288.c
> > > b/drivers/clk/rockchip/clk-rk3288.c index 0df5bae..31c4f78 100644
> > > --- a/drivers/clk/rockchip/clk-rk3288.c
> > > +++ b/drivers/clk/rockchip/clk-rk3288.c
> > > @@ -647,7 +647,7 @@ static struct rockchip_clk_branch
> > > rk3288_clk_branches[]
> > > __initdata = { GATE(0, "pclk_efuse_1024", "pclk_cpu", 0,
> > > RK3288_CLKGATE_CON(11), 2, GFLAGS),
> > out of curiosity, as I haven't found anything about it yet, do you also know
> > what the pclk_efuse_1024 is used for?
> ok, found this myself (the 32x32 bit efuse), but it looks like there is also a
> clock "acc_efuse" - what is this used for?
Sorry, I have not idea too..
> Heiko
>
> > > GATE(PCLK_TZPC, "pclk_tzpc",
> > > "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS), GATE(PCLK_UART2,
> > > "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS), -	
> GATE(0,
> > > "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
> > > +	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0,
> > > RK3288_CLKGATE_CON(11), 10, GFLAGS), GATE(PCLK_RKPWM, "pclk_rkpwm",
> > > "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
> > >
> > >   	/* ddrctrl [DDR Controller PHY clock] gates */
> > >
> > > diff --git a/include/dt-bindings/clock/rk3288-cru.h
> > > b/include/dt-bindings/clock/rk3288-cru.h index c719aac..ab74d5e 100644
> > > --- a/include/dt-bindings/clock/rk3288-cru.h
> > > +++ b/include/dt-bindings/clock/rk3288-cru.h
> > > @@ -164,6 +164,7 @@
> > >
> > >   #define PCLK_DDRUPCTL1		366
> > >   #define PCLK_PUBL1		367
> > >   #define PCLK_WDT		368
> > >
> > > +#define PCLK_EFUSE256		369
> > >
> > >   /* hclk gates */
> > >   #define HCLK_GPS		448


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