Re: [PATCH v10 3/8] add fpga manager core

From: atull
Date: Fri Aug 14 2015 - 11:52:28 EST

On Fri, 14 Aug 2015, atull wrote:

> On Fri, 14 Aug 2015, Moritz Fischer wrote:
> > Hi Alan,
> >
> > I've updated my Zynq driver (it can be found in an older version
> > against your v8 in the Xilinx tree, too)
> >
> >
> Since we are both already using this and have been for a while now, I hope it
> can go up into the mainstream instead of continuing to exist only in Altera
> and Xilinx's git trees.

Hi Moritz,

I fetched your git tree and took a look at your low level driver.

I had a some feedback. write_complete() is a blocking call, waiting for the
FPGA to go into operating state and timing out (ETIMEDOUT) if necessary. The
fpga-mgr.c framework is assuming that when write_complete exits with status 0,
that means that the FPGA is in operating state. That's why it's proper for us
to add "mgr->state = FPGA_MGR_STATE_OPERATING" after write_complete returns
success as you noted. My suggestion is that your write_complete() should check
status in this way. Whatever error codes it returns will get propagated.

Also, I'm wondering how the simple-fpga-bus stuff looks to you now that you've
had it for a little while.

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