[PATCH v2 7/9] rockchip: make sure timer5 is enabled on rk3036 platforms

[Xing Zheng]

The timer5 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.

Signed-off-by: Xing Zheng <zhengxing@xxxxxxxxxxxxxx>
---

Changes in v2: None

 arch/arm/mach-rockchip/rockchip.c |   22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index b6cf3b4..937047f 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -32,6 +32,8 @@
 #define RK3288_GRF_SOC_CON0 0x244
 #define RK3288_TIMER6_7_PHYS 0xff810000
 
+#define RK3036_TIMER5_PHYS 0x200440a0
+
 static void __init rockchip_timer_init(void)
 {
 	if (of_machine_is_compatible("rockchip,rk3288")) {
@@ -64,6 +66,25 @@ static void __init rockchip_timer_init(void)
 			regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
 		else
 			pr_err("rockchip: could not get grf syscon\n");
+	} else if (of_machine_is_compatible("rockchip,rk3036")) {
+		void __iomem *reg_base;
+
+		/*
+		 * Most/all uboot versions for rk3036 don't enable timer5
+		 * which is needed for the architected timer to work.
+		 * So make sure it is running during early boot.
+		 */
+		reg_base = ioremap(RK3036_TIMER5_PHYS, SZ_16K);
+		if (reg_base) {
+			writel(0, reg_base + 0x10);
+			writel(0xffffffff, reg_base);
+			writel(0xffffffff, reg_base + 0x04);
+			writel(1, reg_base + 0x10);
+			dsb();
+			iounmap(reg_base);
+		} else {
+			pr_err("rockchip: could not map timer5 registers\n");
+		}
 	}
 
 	of_clk_init(NULL);
@@ -79,6 +100,7 @@ static void __init rockchip_dt_init(void)
 
 static const char * const rockchip_board_dt_compat[] = {
 	"rockchip,rk2928",
+	"rockchip,rk3036",
 	"rockchip,rk3066a",
 	"rockchip,rk3066b",
 	"rockchip,rk3188",
-- 
1.7.9.5


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