Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management module driver

[Barry Song]

2015-10-05 16:21 GMT+08:00 Lee Jones <lee.jones@xxxxxxxxxx>:
> On Sun, 04 Oct 2015, Barry Song wrote:
>> 2015-09-29 16:55 GMT+08:00 Lee Jones <lee.jones@xxxxxxxxxx>:
>> > On Tue, 29 Sep 2015, Barry Song wrote:
>> >
>> >> 2015-09-29 15:16 GMT+08:00 Lee Jones <lee.jones@xxxxxxxxxx>:
>> >> > On Tue, 29 Sep 2015, Barry Song wrote:
>> >> >> >> >> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
>> >> >> >> >> +{
>> >> >> >> >> +     struct device_node *np = pdev->dev.of_node;
>> >> >> >> >> +     const struct of_device_id *match;
>> >> >> >> >> +     struct sirfsoc_pwrc_info *pwrcinfo;
>> >> >> >> >> +     struct regmap_irq_chip *regmap_irq_chip;
>> >> >> >> >> +     struct sirfsoc_pwrc_register *pwrc_reg;
>> >> >> >> >> +     struct regmap *map;
>> >> >> >> >> +     int ret;
>> >> >> >> >> +     u32 base;
>> >> >> >> >> +
>> >> >> >> >> +     if (of_property_read_u32(np, "reg", &base))
>> >> >> >> >> +             panic("unable to find base address of pwrc node in dtb\n");
>> >> >> >> >
>> >> >> >> > It looks like this driver should depend on OF.
>> >> >> >> >
>> >> >> >> > Why are you obtaining the base address manually? Use:
>> >> >> >> >
>> >> >> >> >   res = platform_get_resource();
>> >> >> >> >   devm_ioremap_resource(res);
>> >> >> >> >
>> >> >> >> > ... instead.
>> >> >> >>
>> >> >> >> this was explained as they are not in memory space, they are behind a
>> >> >> >> bus bridge.
>> >> >> >
>> >> >> > Use 'ranges' in the DT, then you can pull out the proper address
>> >> >> > without hand rolling your own method.
>> >> >>
>> >> >> it seems it is not a "ranges" thing,  things behind rtciobrg is much
>> >> >> like things behind USB or sdio. we need to use a rtciobrg protocol to
>> >> >> do read/write.
>> >> >> they can not be randomly accessed by load/store, and can't be XIP.
>> >> >> they don't have any ranges in CPU memory space.
>> >> >
>> >> > So what's the point of 'base' then?  I assumed this was the base of
>> >> > the IP registers which where memory mapped?
>> >>
>> >> just think we have a i2c device, and this i2c device has multi-functions.
>> >> each function has a base of its register offset.
>> >> actually, the base is the offset of 1st register.
>> >
>> > Does it every change, from device to device?
>
> What I mean is ...

i get you now :-)

>
>> yes. Lee. e.g:
>>
>>                         rtc-iobg@18840000 {
>>                                 reg = <0x18840000 0x1000>;
>>
>>                                 sysrtc@2000 {
>
> Is sysrtc always @2000, or might it be @4000 on some devices?


that depends on the IC design. technically, they can be anywhere and
in any order behind rtc-iobridge.
good luck is the existing SoCs such as prima2, atlas6, atlas7 all put
it at 2000.

>
>>                                         compatible = "sirf,prima2-sysrtc";
>>                                         reg = <0x2000 0x100>;
>>                                         interrupts = <0 52 0>;
>>                                 };
>>                                 pwrc@3000 {
>
> Same for pwrc?

all of the existing prima2, atlas6, atlas7 chips put it at 3000. so
the problem is it a hardware OF property or a const/MARCO?
i feel it is a OF property. it is pretty much similar with we can put
a i2c, spi ,usb controller in different memory place in memory bus.

>
>>                                         compatible = "sirf,atlas7-pwrc";
>>                                         reg = <0x3000 0x100>;
>>                                         interrupts = <0 32 0>;
>>                                 };
>>
>>                         }
>>

-barry
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