[PATCH 11/16] perf tests: Move x86 tests into arch directory

From: Arnaldo Carvalho de Melo
Date: Mon Oct 05 2015 - 17:05:28 EST

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From: Matt Fleming <matt.fleming@xxxxxxxxx>

Move out the x86-specific tests into tools/perf/arch/x86/tests and
define an 'arch_tests' array, which is the list of tests that only apply
to the build architecture.

We can also now begin to get rid of some of the #ifdef code that is
present in the generic perf tests.

Signed-off-by: Matt Fleming <matt.fleming@xxxxxxxxx>
Cc: Adrian Hunter <adrian.hunter@xxxxxxxxx>
Cc: Andi Kleen <ak@xxxxxxxxxxxxxxx>
Cc: Fenghua Yu <fenghua.yu@xxxxxxxxx>
Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
Cc: Kanaka Juvva <kanaka.d.juvva@xxxxxxxxx>
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Vikas Shivappa <vikas.shivappa@xxxxxxxxx>
Cc: Vince Weaver <vince@xxxxxxxxxx>
Link: http://lkml.kernel.org/n/tip-9s68h4ptg06ah0lgnjz55mqn@xxxxxxxxxxxxxx
Signed-off-by: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
---
tools/perf/arch/x86/include/arch-tests.h | 12 +
tools/perf/arch/x86/tests/Build | 3 +
tools/perf/arch/x86/tests/arch-tests.c | 20 +
tools/perf/arch/x86/tests/dwarf-unwind.c | 1 +
tools/perf/arch/x86/tests/gen-insn-x86-dat.awk | 75 +++
tools/perf/arch/x86/tests/gen-insn-x86-dat.sh | 43 ++
tools/perf/arch/x86/tests/insn-x86-dat-32.c | 658 +++++++++++++++++++
tools/perf/arch/x86/tests/insn-x86-dat-64.c | 768 ++++++++++++++++++++++
tools/perf/arch/x86/tests/insn-x86-dat-src.c | 877 +++++++++++++++++++++++++
tools/perf/arch/x86/tests/insn-x86.c | 185 ++++++
tools/perf/arch/x86/tests/perf-time-to-tsc.c | 164 +++++
tools/perf/arch/x86/tests/rdpmc.c | 174 +++++
tools/perf/tests/Build | 6 -
tools/perf/tests/builtin-test.c | 28 -
tools/perf/tests/dwarf-unwind.c | 4 +
tools/perf/tests/gen-insn-x86-dat.awk | 75 ---
tools/perf/tests/gen-insn-x86-dat.sh | 43 --
tools/perf/tests/insn-x86-dat-32.c | 658 -------------------
tools/perf/tests/insn-x86-dat-64.c | 768 ----------------------
tools/perf/tests/insn-x86-dat-src.c | 877 -------------------------
tools/perf/tests/insn-x86.c | 184 ------
tools/perf/tests/perf-time-to-tsc.c | 162 -----
tools/perf/tests/rdpmc.c | 177 -----
tools/perf/tests/tests.h | 5 +-
24 files changed, 2985 insertions(+), 2982 deletions(-)
create mode 100644 tools/perf/arch/x86/tests/gen-insn-x86-dat.awk
create mode 100755 tools/perf/arch/x86/tests/gen-insn-x86-dat.sh
create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-32.c
create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-64.c
create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-src.c
create mode 100644 tools/perf/arch/x86/tests/insn-x86.c
create mode 100644 tools/perf/arch/x86/tests/perf-time-to-tsc.c
create mode 100644 tools/perf/arch/x86/tests/rdpmc.c
delete mode 100644 tools/perf/tests/gen-insn-x86-dat.awk
delete mode 100755 tools/perf/tests/gen-insn-x86-dat.sh
delete mode 100644 tools/perf/tests/insn-x86-dat-32.c
delete mode 100644 tools/perf/tests/insn-x86-dat-64.c
delete mode 100644 tools/perf/tests/insn-x86-dat-src.c
delete mode 100644 tools/perf/tests/insn-x86.c
delete mode 100644 tools/perf/tests/perf-time-to-tsc.c
delete mode 100644 tools/perf/tests/rdpmc.c

diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86/include/arch-tests.h
index 4bd41d8e1ca4..5927cf224325 100644
--- a/tools/perf/arch/x86/include/arch-tests.h
+++ b/tools/perf/arch/x86/include/arch-tests.h
@@ -1,6 +1,18 @@
#ifndef ARCH_TESTS_H
#define ARCH_TESTS_H

+/* Tests */
+int test__rdpmc(void);
+int test__perf_time_to_tsc(void);
+int test__insn_x86(void);
+
+#ifdef HAVE_DWARF_UNWIND_SUPPORT
+struct thread;
+struct perf_sample;
+int test__arch_unwind_sample(struct perf_sample *sample,
+ struct thread *thread);
+#endif
+
extern struct test arch_tests[];

#endif
diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build
index d827ef384b33..8e2c5a38c3b9 100644
--- a/tools/perf/arch/x86/tests/Build
+++ b/tools/perf/arch/x86/tests/Build
@@ -2,3 +2,6 @@ libperf-$(CONFIG_DWARF_UNWIND) += regs_load.o
libperf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o

libperf-y += arch-tests.o
+libperf-y += rdpmc.o
+libperf-y += perf-time-to-tsc.o
+libperf-$(CONFIG_AUXTRACE) += insn-x86.o
diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c
index fca9eb9d39a2..d116c217af99 100644
--- a/tools/perf/arch/x86/tests/arch-tests.c
+++ b/tools/perf/arch/x86/tests/arch-tests.c
@@ -4,6 +4,26 @@

struct test arch_tests[] = {
{
+ .desc = "x86 rdpmc test",
+ .func = test__rdpmc,
+ },
+ {
+ .desc = "Test converting perf time to TSC",
+ .func = test__perf_time_to_tsc,
+ },
+#ifdef HAVE_DWARF_UNWIND_SUPPORT
+ {
+ .desc = "Test dwarf unwind",
+ .func = test__dwarf_unwind,
+ },
+#endif
+#ifdef HAVE_AUXTRACE_SUPPORT
+ {
+ .desc = "Test x86 instruction decoder - new instructions",
+ .func = test__insn_x86,
+ },
+#endif
+ {
.func = NULL,
},

diff --git a/tools/perf/arch/x86/tests/dwarf-unwind.c b/tools/perf/arch/x86/tests/dwarf-unwind.c
index d8bbf7ad1681..7f209ce827bf 100644
--- a/tools/perf/arch/x86/tests/dwarf-unwind.c
+++ b/tools/perf/arch/x86/tests/dwarf-unwind.c
@@ -5,6 +5,7 @@
#include "event.h"
#include "debug.h"
#include "tests/tests.h"
+#include "arch-tests.h"

#define STACK_SIZE 8192

diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk
new file mode 100644
index 000000000000..a21454835cd4
--- /dev/null
+++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk
@@ -0,0 +1,75 @@
+#!/bin/awk -f
+# gen-insn-x86-dat.awk: script to convert data for the insn-x86 test
+# Copyright (c) 2015, Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+BEGIN {
+ print "/*"
+ print " * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk"
+ print " * from insn-x86-dat-src.c for inclusion by insn-x86.c"
+ print " * Do not change this code."
+ print "*/\n"
+ op = ""
+ branch = ""
+ rel = 0
+ going = 0
+}
+
+/ Start here / {
+ going = 1
+}
+
+/ Stop here / {
+ going = 0
+}
+
+/^\s*[0-9a-fA-F]+\:/ {
+ if (going) {
+ colon_pos = index($0, ":")
+ useful_line = substr($0, colon_pos + 1)
+ first_pos = match(useful_line, "[0-9a-fA-F]")
+ useful_line = substr(useful_line, first_pos)
+ gsub("\t", "\\t", useful_line)
+ printf "{{"
+ len = 0
+ for (i = 2; i <= NF; i++) {
+ if (match($i, "^[0-9a-fA-F][0-9a-fA-F]$")) {
+ printf "0x%s, ", $i
+ len += 1
+ } else {
+ break
+ }
+ }
+ printf "}, %d, %s, \"%s\", \"%s\",", len, rel, op, branch
+ printf "\n\"%s\",},\n", useful_line
+ op = ""
+ branch = ""
+ rel = 0
+ }
+}
+
+/ Expecting: / {
+ expecting_str = " Expecting: "
+ expecting_len = length(expecting_str)
+ expecting_pos = index($0, expecting_str)
+ useful_line = substr($0, expecting_pos + expecting_len)
+ for (i = 1; i <= NF; i++) {
+ if ($i == "Expecting:") {
+ i++
+ op = $i
+ i++
+ branch = $i
+ i++
+ rel = $i
+ break
+ }
+ }
+}
diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh
new file mode 100755
index 000000000000..2d4ef94cff98
--- /dev/null
+++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+# gen-insn-x86-dat: generate data for the insn-x86 test
+# Copyright (c) 2015, Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+
+set -e
+
+if [ "$(uname -m)" != "x86_64" ]; then
+ echo "ERROR: This script only works on x86_64"
+ exit 1
+fi
+
+cd $(dirname $0)
+
+trap 'echo "Might need a more recent version of binutils"' EXIT
+
+echo "Compiling insn-x86-dat-src.c to 64-bit object"
+
+gcc -g -c insn-x86-dat-src.c
+
+objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-64.c
+
+rm -f insn-x86-dat-src.o
+
+echo "Compiling insn-x86-dat-src.c to 32-bit object"
+
+gcc -g -c -m32 insn-x86-dat-src.c
+
+objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-32.c
+
+rm -f insn-x86-dat-src.o
+
+trap - EXIT
+
+echo "Done (use git diff to see the changes)"
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
new file mode 100644
index 000000000000..3b491cfe204e
--- /dev/null
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c
@@ -0,0 +1,658 @@
+/*
+ * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
+ * from insn-x86-dat-src.c for inclusion by insn-x86.c
+ * Do not change this code.
+*/
+
+{{0x0f, 0x31, }, 2, 0, "", "",
+"0f 31 \trdtsc ",},
+{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
+"f3 0f 1b 00 \tbndmk (%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
+"f3 0f 1b 18 \tbndmk (%eax),%bnd3",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
+"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
+"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
+"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
+"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
+"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%ebp,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"f3 0f 1a 00 \tbndcl (%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1a 05 78 56 34 12 \tbndcl 0x12345678,%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
+"f3 0f 1a 18 \tbndcl (%eax),%bnd3",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
+"f3 0f 1a 04 01 \tbndcl (%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
+"f3 0f 1a 04 08 \tbndcl (%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
+"f3 0f 1a 04 c8 \tbndcl (%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
+"f3 0f 1a 40 12 \tbndcl 0x12(%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
+"f3 0f 1a 45 12 \tbndcl 0x12(%ebp),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 01 12 \tbndcl 0x12(%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 05 12 \tbndcl 0x12(%ebp,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 08 12 \tbndcl 0x12(%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 c8 12 \tbndcl 0x12(%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%eax),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%ebp),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%ecx,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%ebp,%eax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%eax,%ecx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%eax,%ecx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
+"f3 0f 1a c0 \tbndcl %eax,%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"f2 0f 1a 00 \tbndcu (%eax),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1a 05 78 56 34 12 \tbndcu 0x12345678,%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
+"f2 0f 1a 18 \tbndcu (%eax),%bnd3",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
+"f2 0f 1a 04 01 \tbndcu (%ecx,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
+"f2 0f 1a 04 08 \tbndcu (%eax,%ecx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
+"f2 0f 1a 04 c8 \tbndcu (%eax,%ecx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
+"f2 0f 1a 40 12 \tbndcu 0x12(%eax),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
+"f2 0f 1a 45 12 \tbndcu 0x12(%ebp),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 01 12 \tbndcu 0x12(%ecx,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 05 12 \tbndcu 0x12(%ebp,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 08 12 \tbndcu 0x12(%eax,%ecx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 c8 12 \tbndcu 0x12(%eax,%ecx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%eax),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%ebp),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%ecx,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%ebp,%eax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
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+"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%eax),%bnd0",},
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+"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%ebp)",},
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+"0f 1a 04 01 \tbndldx (%ecx,%eax,1),%bnd0",},
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+"0f 1b 04 01 \tbndstx %bnd0,(%ecx,%eax,1)",},
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+"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%eax,1)",},
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+"0f 1b 04 08 \tbndstx %bnd0,(%eax,%ecx,1)",},
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+"0f 1b 40 12 \tbndstx %bnd0,0x12(%eax)",},
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+"0f 1b 45 12 \tbndstx %bnd0,0x12(%ebp)",},
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+"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%ecx,%eax,1)",},
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+"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%eax,%ecx,1)",},
+{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax)",},
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+"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%ecx,%eax,1)",},
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+"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%ebp,%eax,1)",},
+{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%eax,%ecx,1)",},
+{{0xf2, 0xe8, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "call", "unconditional",
+"f2 e8 fc ff ff ff \tbnd call 3c3 <main+0x3c3>",},
+{{0xf2, 0xff, 0x10, }, 3, 0, "call", "indirect",
+"f2 ff 10 \tbnd call *(%eax)",},
+{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
+"f2 c3 \tbnd ret ",},
+{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
+"f2 e9 fc ff ff ff \tbnd jmp 3ce <main+0x3ce>",},
+{{0xf2, 0xe9, 0xfc, 0xff, 0xff, 0xff, }, 6, 0xfffffffc, "jmp", "unconditional",
+"f2 e9 fc ff ff ff \tbnd jmp 3d4 <main+0x3d4>",},
+{{0xf2, 0xff, 0x21, }, 3, 0, "jmp", "indirect",
+"f2 ff 21 \tbnd jmp *(%ecx)",},
+{{0xf2, 0x0f, 0x85, 0xfc, 0xff, 0xff, 0xff, }, 7, 0xfffffffc, "jcc", "conditional",
+"f2 0f 85 fc ff ff ff \tbnd jne 3de <main+0x3de>",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
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+"0f 3a cc d7 91 \tsha1rnds4 $0x91,%xmm7,%xmm2",},
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+"0f 3a cc 00 91 \tsha1rnds4 $0x91,(%eax),%xmm0",},
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+"0f 3a cc 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91 \tsha1rnds4 $0x91,(%eax),%xmm3",},
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+"0f 3a cc 04 01 91 \tsha1rnds4 $0x91,(%ecx,%eax,1),%xmm0",},
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+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%eax,1),%xmm0",},
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+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%eax,%ecx,1),%xmm0",},
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+"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%eax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "",
+"0f 38 cd 04 08 \tsha256msg2 (%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "",
+"0f 38 cd 04 c8 \tsha256msg2 (%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "",
+"0f 38 cd 40 12 \tsha256msg2 0x12(%eax),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "",
+"0f 38 cd 45 12 \tsha256msg2 0x12(%ebp),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 01 12 \tsha256msg2 0x12(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 05 12 \tsha256msg2 0x12(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 08 12 \tsha256msg2 0x12(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%eax,%ecx,8),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%eax),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%ebp),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%ecx,%eax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%ebp,%eax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,8),%xmm0",},
+{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
+"66 0f ae 38 \tclflushopt (%eax)",},
+{{0x66, 0x0f, 0xae, 0x3d, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f ae 3d 78 56 34 12 \tclflushopt 0x12345678",},
+{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%eax,%ecx,8)",},
+{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
+"0f ae 38 \tclflush (%eax)",},
+{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
+"0f ae f8 \tsfence ",},
+{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
+"66 0f ae 30 \tclwb (%eax)",},
+{{0x66, 0x0f, 0xae, 0x35, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f ae 35 78 56 34 12 \tclwb 0x12345678",},
+{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%eax,%ecx,8)",},
+{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
+"0f ae 30 \txsaveopt (%eax)",},
+{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
+"0f ae f0 \tmfence ",},
+{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
+"0f c7 20 \txsavec (%eax)",},
+{{0x0f, 0xc7, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f c7 25 78 56 34 12 \txsavec 0x12345678",},
+{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%eax,%ecx,8)",},
+{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
+"0f c7 28 \txsaves (%eax)",},
+{{0x0f, 0xc7, 0x2d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f c7 2d 78 56 34 12 \txsaves 0x12345678",},
+{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%eax,%ecx,8)",},
+{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
+"0f c7 18 \txrstors (%eax)",},
+{{0x0f, 0xc7, 0x1d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f c7 1d 78 56 34 12 \txrstors 0x12345678",},
+{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%eax,%ecx,8)",},
+{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
+"66 0f ae f8 \tpcommit ",},
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-64.c b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
new file mode 100644
index 000000000000..4fe7cce179c4
--- /dev/null
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-64.c
@@ -0,0 +1,768 @@
+/*
+ * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
+ * from insn-x86-dat-src.c for inclusion by insn-x86.c
+ * Do not change this code.
+*/
+
+{{0x0f, 0x31, }, 2, 0, "", "",
+"0f 31 \trdtsc ",},
+{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
+"f3 0f 1b 00 \tbndmk (%rax),%bnd0",},
+{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
+"f3 41 0f 1b 00 \tbndmk (%r8),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 04 25 78 56 34 12 \tbndmk 0x12345678,%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
+"f3 0f 1b 18 \tbndmk (%rax),%bnd3",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
+"f3 0f 1b 04 01 \tbndmk (%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
+"f3 0f 1b 04 08 \tbndmk (%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
+"f3 0f 1b 04 c8 \tbndmk (%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
+"f3 0f 1b 40 12 \tbndmk 0x12(%rax),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
+"f3 0f 1b 45 12 \tbndmk 0x12(%rbp),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 01 12 \tbndmk 0x12(%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 05 12 \tbndmk 0x12(%rbp,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 08 12 \tbndmk 0x12(%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f3 0f 1b 44 c8 12 \tbndmk 0x12(%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%rax),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%rbp),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"f3 0f 1a 00 \tbndcl (%rax),%bnd0",},
+{{0xf3, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
+"f3 41 0f 1a 00 \tbndcl (%r8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 04 25 78 56 34 12 \tbndcl 0x12345678,%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
+"f3 0f 1a 18 \tbndcl (%rax),%bnd3",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
+"f3 0f 1a 04 01 \tbndcl (%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
+"f3 0f 1a 04 08 \tbndcl (%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
+"f3 0f 1a 04 c8 \tbndcl (%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
+"f3 0f 1a 40 12 \tbndcl 0x12(%rax),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
+"f3 0f 1a 45 12 \tbndcl 0x12(%rbp),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 01 12 \tbndcl 0x12(%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 05 12 \tbndcl 0x12(%rbp,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 08 12 \tbndcl 0x12(%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f3 0f 1a 44 c8 12 \tbndcl 0x12(%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%rax),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%rbp),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,8),%bnd0",},
+{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
+"f3 0f 1a c0 \tbndcl %rax,%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"f2 0f 1a 00 \tbndcu (%rax),%bnd0",},
+{{0xf2, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
+"f2 41 0f 1a 00 \tbndcu (%r8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 04 25 78 56 34 12 \tbndcu 0x12345678,%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
+"f2 0f 1a 18 \tbndcu (%rax),%bnd3",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
+"f2 0f 1a 04 01 \tbndcu (%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
+"f2 0f 1a 04 08 \tbndcu (%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
+"f2 0f 1a 04 c8 \tbndcu (%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
+"f2 0f 1a 40 12 \tbndcu 0x12(%rax),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
+"f2 0f 1a 45 12 \tbndcu 0x12(%rbp),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 01 12 \tbndcu 0x12(%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 05 12 \tbndcu 0x12(%rbp,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 08 12 \tbndcu 0x12(%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f2 0f 1a 44 c8 12 \tbndcu 0x12(%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%rax),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%rbp),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
+"f2 0f 1a c0 \tbndcu %rax,%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
+"f2 0f 1b 00 \tbndcn (%rax),%bnd0",},
+{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
+"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
+"f2 0f 1b 18 \tbndcn (%rax),%bnd3",},
+{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
+"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
+"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
+"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
+"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
+"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",},
+{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "",
+"f2 0f 1b c0 \tbndcn %rax,%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"66 0f 1a 00 \tbndmov (%rax),%bnd0",},
+{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
+"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
+"66 0f 1a 18 \tbndmov (%rax),%bnd3",},
+{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
+"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
+"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
+"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
+"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
+"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",},
+{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
+"66 0f 1b 00 \tbndmov %bnd0,(%rax)",},
+{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
+"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",},
+{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",},
+{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
+"66 0f 1b 18 \tbndmov %bnd3,(%rax)",},
+{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
+"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
+"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",},
+{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
+"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",},
+{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
+"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",},
+{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
+"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",},
+{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",},
+{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",},
+{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",},
+{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",},
+{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp,%rax,1)",},
+{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,1)",},
+{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,8)",},
+{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "",
+"66 0f 1a c8 \tbndmov %bnd0,%bnd1",},
+{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "",
+"66 0f 1a c1 \tbndmov %bnd1,%bnd0",},
+{{0x0f, 0x1a, 0x00, }, 3, 0, "", "",
+"0f 1a 00 \tbndldx (%rax),%bnd0",},
+{{0x41, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
+"41 0f 1a 00 \tbndldx (%r8),%bnd0",},
+{{0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1a 04 25 78 56 34 12 \tbndldx 0x12345678,%bnd0",},
+{{0x0f, 0x1a, 0x18, }, 3, 0, "", "",
+"0f 1a 18 \tbndldx (%rax),%bnd3",},
+{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "",
+"0f 1a 04 01 \tbndldx (%rcx,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "",
+"0f 1a 04 08 \tbndldx (%rax,%rcx,1),%bnd0",},
+{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "",
+"0f 1a 40 12 \tbndldx 0x12(%rax),%bnd0",},
+{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "",
+"0f 1a 45 12 \tbndldx 0x12(%rbp),%bnd0",},
+{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "",
+"0f 1a 44 01 12 \tbndldx 0x12(%rcx,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "",
+"0f 1a 44 05 12 \tbndldx 0x12(%rbp,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "",
+"0f 1a 44 08 12 \tbndldx 0x12(%rax,%rcx,1),%bnd0",},
+{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%rax),%bnd0",},
+{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%rbp),%bnd0",},
+{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%rcx,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1a 84 05 78 56 34 12 \tbndldx 0x12345678(%rbp,%rax,1),%bnd0",},
+{{0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1a 84 08 78 56 34 12 \tbndldx 0x12345678(%rax,%rcx,1),%bnd0",},
+{{0x0f, 0x1b, 0x00, }, 3, 0, "", "",
+"0f 1b 00 \tbndstx %bnd0,(%rax)",},
+{{0x41, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
+"41 0f 1b 00 \tbndstx %bnd0,(%r8)",},
+{{0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 04 25 78 56 34 12 \tbndstx %bnd0,0x12345678",},
+{{0x0f, 0x1b, 0x18, }, 3, 0, "", "",
+"0f 1b 18 \tbndstx %bnd3,(%rax)",},
+{{0x0f, 0x1b, 0x04, 0x01, }, 4, 0, "", "",
+"0f 1b 04 01 \tbndstx %bnd0,(%rcx,%rax,1)",},
+{{0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%rax,1)",},
+{{0x0f, 0x1b, 0x04, 0x08, }, 4, 0, "", "",
+"0f 1b 04 08 \tbndstx %bnd0,(%rax,%rcx,1)",},
+{{0x0f, 0x1b, 0x40, 0x12, }, 4, 0, "", "",
+"0f 1b 40 12 \tbndstx %bnd0,0x12(%rax)",},
+{{0x0f, 0x1b, 0x45, 0x12, }, 4, 0, "", "",
+"0f 1b 45 12 \tbndstx %bnd0,0x12(%rbp)",},
+{{0x0f, 0x1b, 0x44, 0x01, 0x12, }, 5, 0, "", "",
+"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%rcx,%rax,1)",},
+{{0x0f, 0x1b, 0x44, 0x05, 0x12, }, 5, 0, "", "",
+"0f 1b 44 05 12 \tbndstx %bnd0,0x12(%rbp,%rax,1)",},
+{{0x0f, 0x1b, 0x44, 0x08, 0x12, }, 5, 0, "", "",
+"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%rax,%rcx,1)",},
+{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax)",},
+{{0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
+"0f 1b 85 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp)",},
+{{0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%rcx,%rax,1)",},
+{{0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp,%rax,1)",},
+{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",},
+{{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional",
+"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",},
+{{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
+"67 f2 ff 10 \tbnd callq *(%eax)",},
+{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
+"f2 c3 \tbnd retq ",},
+{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
+"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",},
+{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
+"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",},
+{{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect",
+"67 f2 ff 21 \tbnd jmpq *(%ecx)",},
+{{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional",
+"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",},
+{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
+"0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
+"0f 3a cc d7 91 \tsha1rnds4 $0x91,%xmm7,%xmm2",},
+{{0x41, 0x0f, 0x3a, 0xcc, 0xc0, 0x91, }, 6, 0, "", "",
+"41 0f 3a cc c0 91 \tsha1rnds4 $0x91,%xmm8,%xmm0",},
+{{0x44, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
+"44 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm7,%xmm8",},
+{{0x45, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
+"45 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm15,%xmm8",},
+{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
+"0f 3a cc 00 91 \tsha1rnds4 $0x91,(%rax),%xmm0",},
+{{0x41, 0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 6, 0, "", "",
+"41 0f 3a cc 00 91 \tsha1rnds4 $0x91,(%r8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 25 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678,%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x18, 0x91, }, 5, 0, "", "",
+"0f 3a cc 18 91 \tsha1rnds4 $0x91,(%rax),%xmm3",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x01, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 01 91 \tsha1rnds4 $0x91,(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 04 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0x08, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 08 91 \tsha1rnds4 $0x91,(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x04, 0xc8, 0x91, }, 6, 0, "", "",
+"0f 3a cc 04 c8 91 \tsha1rnds4 $0x91,(%rax,%rcx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x40, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 40 12 91 \tsha1rnds4 $0x91,0x12(%rax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x45, 0x12, 0x91, }, 6, 0, "", "",
+"0f 3a cc 45 12 91 \tsha1rnds4 $0x91,0x12(%rbp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x01, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 01 12 91 \tsha1rnds4 $0x91,0x12(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x05, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 05 12 91 \tsha1rnds4 $0x91,0x12(%rbp,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0x08, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 08 12 91 \tsha1rnds4 $0x91,0x12(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x44, 0xc8, 0x12, 0x91, }, 7, 0, "", "",
+"0f 3a cc 44 c8 12 91 \tsha1rnds4 $0x91,0x12(%rax,%rcx,8),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 80 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rax),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, 0x91, }, 9, 0, "", "",
+"0f 3a cc 85 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rbp),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 01 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 05 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rbp,%rax,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 08 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x3a, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x91, }, 10, 0, "", "",
+"0f 3a cc 84 c8 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rax,%rcx,8),%xmm0",},
+{{0x44, 0x0f, 0x3a, 0xcc, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, 0x91, }, 11, 0, "", "",
+"44 0f 3a cc bc c8 78 56 34 12 91 \tsha1rnds4 $0x91,0x12345678(%rax,%rcx,8),%xmm15",},
+{{0x0f, 0x38, 0xc8, 0xc1, }, 4, 0, "", "",
+"0f 38 c8 c1 \tsha1nexte %xmm1,%xmm0",},
+{{0x0f, 0x38, 0xc8, 0xd7, }, 4, 0, "", "",
+"0f 38 c8 d7 \tsha1nexte %xmm7,%xmm2",},
+{{0x41, 0x0f, 0x38, 0xc8, 0xc0, }, 5, 0, "", "",
+"41 0f 38 c8 c0 \tsha1nexte %xmm8,%xmm0",},
+{{0x44, 0x0f, 0x38, 0xc8, 0xc7, }, 5, 0, "", "",
+"44 0f 38 c8 c7 \tsha1nexte %xmm7,%xmm8",},
+{{0x45, 0x0f, 0x38, 0xc8, 0xc7, }, 5, 0, "", "",
+"45 0f 38 c8 c7 \tsha1nexte %xmm15,%xmm8",},
+{{0x0f, 0x38, 0xc8, 0x00, }, 4, 0, "", "",
+"0f 38 c8 00 \tsha1nexte (%rax),%xmm0",},
+{{0x41, 0x0f, 0x38, 0xc8, 0x00, }, 5, 0, "", "",
+"41 0f 38 c8 00 \tsha1nexte (%r8),%xmm0",},
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+"0f 38 cc 84 01 78 56 34 12 \tsha256msg1 0x12345678(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cc 84 05 78 56 34 12 \tsha256msg1 0x12345678(%rbp,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cc 84 08 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x38, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cc 84 c8 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,8),%xmm0",},
+{{0x44, 0x0f, 0x38, 0xcc, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
+"44 0f 38 cc bc c8 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,8),%xmm15",},
+{{0x0f, 0x38, 0xcd, 0xc1, }, 4, 0, "", "",
+"0f 38 cd c1 \tsha256msg2 %xmm1,%xmm0",},
+{{0x0f, 0x38, 0xcd, 0xd7, }, 4, 0, "", "",
+"0f 38 cd d7 \tsha256msg2 %xmm7,%xmm2",},
+{{0x41, 0x0f, 0x38, 0xcd, 0xc0, }, 5, 0, "", "",
+"41 0f 38 cd c0 \tsha256msg2 %xmm8,%xmm0",},
+{{0x44, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
+"44 0f 38 cd c7 \tsha256msg2 %xmm7,%xmm8",},
+{{0x45, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
+"45 0f 38 cd c7 \tsha256msg2 %xmm15,%xmm8",},
+{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "",
+"0f 38 cd 00 \tsha256msg2 (%rax),%xmm0",},
+{{0x41, 0x0f, 0x38, 0xcd, 0x00, }, 5, 0, "", "",
+"41 0f 38 cd 00 \tsha256msg2 (%r8),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 04 25 78 56 34 12 \tsha256msg2 0x12345678,%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "",
+"0f 38 cd 18 \tsha256msg2 (%rax),%xmm3",},
+{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "",
+"0f 38 cd 04 01 \tsha256msg2 (%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "",
+"0f 38 cd 04 08 \tsha256msg2 (%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "",
+"0f 38 cd 04 c8 \tsha256msg2 (%rax,%rcx,8),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "",
+"0f 38 cd 40 12 \tsha256msg2 0x12(%rax),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "",
+"0f 38 cd 45 12 \tsha256msg2 0x12(%rbp),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 01 12 \tsha256msg2 0x12(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 05 12 \tsha256msg2 0x12(%rbp,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 08 12 \tsha256msg2 0x12(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
+"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%rax,%rcx,8),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%rax),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%rbp),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%rcx,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%rbp,%rax,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,1),%xmm0",},
+{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm0",},
+{{0x44, 0x0f, 0x38, 0xcd, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
+"44 0f 38 cd bc c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm15",},
+{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
+"66 0f ae 38 \tclflushopt (%rax)",},
+{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "",
+"66 41 0f ae 38 \tclflushopt (%r8)",},
+{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",},
+{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",},
+{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
+"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",},
+{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
+"0f ae 38 \tclflush (%rax)",},
+{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
+"41 0f ae 38 \tclflush (%r8)",},
+{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
+"0f ae f8 \tsfence ",},
+{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
+"66 0f ae 30 \tclwb (%rax)",},
+{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",
+"66 41 0f ae 30 \tclwb (%r8)",},
+{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",},
+{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",},
+{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
+"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",},
+{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
+"0f ae 30 \txsaveopt (%rax)",},
+{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
+"41 0f ae 30 \txsaveopt (%r8)",},
+{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
+"0f ae f0 \tmfence ",},
+{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
+"0f c7 20 \txsavec (%rax)",},
+{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "",
+"41 0f c7 20 \txsavec (%r8)",},
+{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",},
+{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",},
+{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",},
+{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
+"0f c7 28 \txsaves (%rax)",},
+{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "",
+"41 0f c7 28 \txsaves (%r8)",},
+{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",},
+{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",},
+{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",},
+{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
+"0f c7 18 \txrstors (%rax)",},
+{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "",
+"41 0f c7 18 \txrstors (%r8)",},
+{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",},
+{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
+"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",},
+{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
+"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",},
+{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
+"66 0f ae f8 \tpcommit ",},
diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
new file mode 100644
index 000000000000..41b1b1c62660
--- /dev/null
+++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c
@@ -0,0 +1,877 @@
+/*
+ * This file contains instructions for testing by the test titled:
+ *
+ * "Test x86 instruction decoder - new instructions"
+ *
+ * Note that the 'Expecting' comment lines are consumed by the
+ * gen-insn-x86-dat.awk script and have the format:
+ *
+ * Expecting: <op> <branch> <rel>
+ *
+ * If this file is changed, remember to run the gen-insn-x86-dat.sh
+ * script and commit the result.
+ *
+ * Refer to insn-x86.c for more details.
+ */
+
+int main(void)
+{
+ /* Following line is a marker for the awk script - do not change */
+ asm volatile("rdtsc"); /* Start here */
+
+#ifdef __x86_64__
+
+ /* bndmk m64, bnd */
+
+ asm volatile("bndmk (%rax), %bnd0");
+ asm volatile("bndmk (%r8), %bnd0");
+ asm volatile("bndmk (0x12345678), %bnd0");
+ asm volatile("bndmk (%rax), %bnd3");
+ asm volatile("bndmk (%rcx,%rax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndmk (%rax,%rcx,1), %bnd0");
+ asm volatile("bndmk (%rax,%rcx,8), %bnd0");
+ asm volatile("bndmk 0x12(%rax), %bnd0");
+ asm volatile("bndmk 0x12(%rbp), %bnd0");
+ asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0");
+ asm volatile("bndmk 0x12345678(%rax), %bnd0");
+ asm volatile("bndmk 0x12345678(%rbp), %bnd0");
+ asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0");
+
+ /* bndcl r/m64, bnd */
+
+ asm volatile("bndcl (%rax), %bnd0");
+ asm volatile("bndcl (%r8), %bnd0");
+ asm volatile("bndcl (0x12345678), %bnd0");
+ asm volatile("bndcl (%rax), %bnd3");
+ asm volatile("bndcl (%rcx,%rax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndcl (%rax,%rcx,1), %bnd0");
+ asm volatile("bndcl (%rax,%rcx,8), %bnd0");
+ asm volatile("bndcl 0x12(%rax), %bnd0");
+ asm volatile("bndcl 0x12(%rbp), %bnd0");
+ asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcl 0x12345678(%rax), %bnd0");
+ asm volatile("bndcl 0x12345678(%rbp), %bnd0");
+ asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcl %rax, %bnd0");
+
+ /* bndcu r/m64, bnd */
+
+ asm volatile("bndcu (%rax), %bnd0");
+ asm volatile("bndcu (%r8), %bnd0");
+ asm volatile("bndcu (0x12345678), %bnd0");
+ asm volatile("bndcu (%rax), %bnd3");
+ asm volatile("bndcu (%rcx,%rax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndcu (%rax,%rcx,1), %bnd0");
+ asm volatile("bndcu (%rax,%rcx,8), %bnd0");
+ asm volatile("bndcu 0x12(%rax), %bnd0");
+ asm volatile("bndcu 0x12(%rbp), %bnd0");
+ asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcu 0x12345678(%rax), %bnd0");
+ asm volatile("bndcu 0x12345678(%rbp), %bnd0");
+ asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcu %rax, %bnd0");
+
+ /* bndcn r/m64, bnd */
+
+ asm volatile("bndcn (%rax), %bnd0");
+ asm volatile("bndcn (%r8), %bnd0");
+ asm volatile("bndcn (0x12345678), %bnd0");
+ asm volatile("bndcn (%rax), %bnd3");
+ asm volatile("bndcn (%rcx,%rax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndcn (%rax,%rcx,1), %bnd0");
+ asm volatile("bndcn (%rax,%rcx,8), %bnd0");
+ asm volatile("bndcn 0x12(%rax), %bnd0");
+ asm volatile("bndcn 0x12(%rbp), %bnd0");
+ asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcn 0x12345678(%rax), %bnd0");
+ asm volatile("bndcn 0x12345678(%rbp), %bnd0");
+ asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0");
+ asm volatile("bndcn %rax, %bnd0");
+
+ /* bndmov m128, bnd */
+
+ asm volatile("bndmov (%rax), %bnd0");
+ asm volatile("bndmov (%r8), %bnd0");
+ asm volatile("bndmov (0x12345678), %bnd0");
+ asm volatile("bndmov (%rax), %bnd3");
+ asm volatile("bndmov (%rcx,%rax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndmov (%rax,%rcx,1), %bnd0");
+ asm volatile("bndmov (%rax,%rcx,8), %bnd0");
+ asm volatile("bndmov 0x12(%rax), %bnd0");
+ asm volatile("bndmov 0x12(%rbp), %bnd0");
+ asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0");
+ asm volatile("bndmov 0x12345678(%rax), %bnd0");
+ asm volatile("bndmov 0x12345678(%rbp), %bnd0");
+ asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0");
+
+ /* bndmov bnd, m128 */
+
+ asm volatile("bndmov %bnd0, (%rax)");
+ asm volatile("bndmov %bnd0, (%r8)");
+ asm volatile("bndmov %bnd0, (0x12345678)");
+ asm volatile("bndmov %bnd3, (%rax)");
+ asm volatile("bndmov %bnd0, (%rcx,%rax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)");
+ asm volatile("bndmov %bnd0, (%rax,%rcx,1)");
+ asm volatile("bndmov %bnd0, (%rax,%rcx,8)");
+ asm volatile("bndmov %bnd0, 0x12(%rax)");
+ asm volatile("bndmov %bnd0, 0x12(%rbp)");
+ asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)");
+ asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)");
+ asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)");
+ asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rax)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rbp)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)");
+
+ /* bndmov bnd2, bnd1 */
+
+ asm volatile("bndmov %bnd0, %bnd1");
+ asm volatile("bndmov %bnd1, %bnd0");
+
+ /* bndldx mib, bnd */
+
+ asm volatile("bndldx (%rax), %bnd0");
+ asm volatile("bndldx (%r8), %bnd0");
+ asm volatile("bndldx (0x12345678), %bnd0");
+ asm volatile("bndldx (%rax), %bnd3");
+ asm volatile("bndldx (%rcx,%rax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(,%rax,1), %bnd0");
+ asm volatile("bndldx (%rax,%rcx,1), %bnd0");
+ asm volatile("bndldx 0x12(%rax), %bnd0");
+ asm volatile("bndldx 0x12(%rbp), %bnd0");
+ asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0");
+ asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0");
+ asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%rax), %bnd0");
+ asm volatile("bndldx 0x12345678(%rbp), %bnd0");
+ asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0");
+
+ /* bndstx bnd, mib */
+
+ asm volatile("bndstx %bnd0, (%rax)");
+ asm volatile("bndstx %bnd0, (%r8)");
+ asm volatile("bndstx %bnd0, (0x12345678)");
+ asm volatile("bndstx %bnd3, (%rax)");
+ asm volatile("bndstx %bnd0, (%rcx,%rax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)");
+ asm volatile("bndstx %bnd0, (%rax,%rcx,1)");
+ asm volatile("bndstx %bnd0, 0x12(%rax)");
+ asm volatile("bndstx %bnd0, 0x12(%rbp)");
+ asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)");
+ asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)");
+ asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%rax)");
+ asm volatile("bndstx %bnd0, 0x12345678(%rbp)");
+ asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)");
+
+ /* bnd prefix on call, ret, jmp and all jcc */
+
+ asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */
+ asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
+ asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
+ asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
+ asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
+ asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
+ asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */
+
+ /* sha1rnds4 imm8, xmm2/m128, xmm1 */
+
+ asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
+ asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
+ asm volatile("sha1rnds4 $0x91, %xmm8, %xmm0");
+ asm volatile("sha1rnds4 $0x91, %xmm7, %xmm8");
+ asm volatile("sha1rnds4 $0x91, %xmm15, %xmm8");
+ asm volatile("sha1rnds4 $0x91, (%rax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%r8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%rax), %xmm3");
+ asm volatile("sha1rnds4 $0x91, (%rcx,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%rax,%rcx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%rax,%rcx,8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rbp), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha1nexte xmm2/m128, xmm1 */
+
+ asm volatile("sha1nexte %xmm1, %xmm0");
+ asm volatile("sha1nexte %xmm7, %xmm2");
+ asm volatile("sha1nexte %xmm8, %xmm0");
+ asm volatile("sha1nexte %xmm7, %xmm8");
+ asm volatile("sha1nexte %xmm15, %xmm8");
+ asm volatile("sha1nexte (%rax), %xmm0");
+ asm volatile("sha1nexte (%r8), %xmm0");
+ asm volatile("sha1nexte (0x12345678), %xmm0");
+ asm volatile("sha1nexte (%rax), %xmm3");
+ asm volatile("sha1nexte (%rcx,%rax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha1nexte (%rax,%rcx,1), %xmm0");
+ asm volatile("sha1nexte (%rax,%rcx,8), %xmm0");
+ asm volatile("sha1nexte 0x12(%rax), %xmm0");
+ asm volatile("sha1nexte 0x12(%rbp), %xmm0");
+ asm volatile("sha1nexte 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rax), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rbp), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha1msg1 xmm2/m128, xmm1 */
+
+ asm volatile("sha1msg1 %xmm1, %xmm0");
+ asm volatile("sha1msg1 %xmm7, %xmm2");
+ asm volatile("sha1msg1 %xmm8, %xmm0");
+ asm volatile("sha1msg1 %xmm7, %xmm8");
+ asm volatile("sha1msg1 %xmm15, %xmm8");
+ asm volatile("sha1msg1 (%rax), %xmm0");
+ asm volatile("sha1msg1 (%r8), %xmm0");
+ asm volatile("sha1msg1 (0x12345678), %xmm0");
+ asm volatile("sha1msg1 (%rax), %xmm3");
+ asm volatile("sha1msg1 (%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha1msg1 (%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg1 (%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg1 0x12(%rax), %xmm0");
+ asm volatile("sha1msg1 0x12(%rbp), %xmm0");
+ asm volatile("sha1msg1 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rax), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rbp), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha1msg2 xmm2/m128, xmm1 */
+
+ asm volatile("sha1msg2 %xmm1, %xmm0");
+ asm volatile("sha1msg2 %xmm7, %xmm2");
+ asm volatile("sha1msg2 %xmm8, %xmm0");
+ asm volatile("sha1msg2 %xmm7, %xmm8");
+ asm volatile("sha1msg2 %xmm15, %xmm8");
+ asm volatile("sha1msg2 (%rax), %xmm0");
+ asm volatile("sha1msg2 (%r8), %xmm0");
+ asm volatile("sha1msg2 (0x12345678), %xmm0");
+ asm volatile("sha1msg2 (%rax), %xmm3");
+ asm volatile("sha1msg2 (%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha1msg2 (%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg2 (%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg2 0x12(%rax), %xmm0");
+ asm volatile("sha1msg2 0x12(%rbp), %xmm0");
+ asm volatile("sha1msg2 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rax), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rbp), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
+ /* Note sha256rnds2 has an implicit operand 'xmm0' */
+
+ asm volatile("sha256rnds2 %xmm4, %xmm1");
+ asm volatile("sha256rnds2 %xmm7, %xmm2");
+ asm volatile("sha256rnds2 %xmm8, %xmm1");
+ asm volatile("sha256rnds2 %xmm7, %xmm8");
+ asm volatile("sha256rnds2 %xmm15, %xmm8");
+ asm volatile("sha256rnds2 (%rax), %xmm1");
+ asm volatile("sha256rnds2 (%r8), %xmm1");
+ asm volatile("sha256rnds2 (0x12345678), %xmm1");
+ asm volatile("sha256rnds2 (%rax), %xmm3");
+ asm volatile("sha256rnds2 (%rcx,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 (%rax,%rcx,1), %xmm1");
+ asm volatile("sha256rnds2 (%rax,%rcx,8), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rax), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rbp), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rcx,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rbp,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rax,%rcx,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%rax,%rcx,8), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rax), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rbp), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rcx,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rbp,%rax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rax,%rcx,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha256msg1 xmm2/m128, xmm1 */
+
+ asm volatile("sha256msg1 %xmm1, %xmm0");
+ asm volatile("sha256msg1 %xmm7, %xmm2");
+ asm volatile("sha256msg1 %xmm8, %xmm0");
+ asm volatile("sha256msg1 %xmm7, %xmm8");
+ asm volatile("sha256msg1 %xmm15, %xmm8");
+ asm volatile("sha256msg1 (%rax), %xmm0");
+ asm volatile("sha256msg1 (%r8), %xmm0");
+ asm volatile("sha256msg1 (0x12345678), %xmm0");
+ asm volatile("sha256msg1 (%rax), %xmm3");
+ asm volatile("sha256msg1 (%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha256msg1 (%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg1 (%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg1 0x12(%rax), %xmm0");
+ asm volatile("sha256msg1 0x12(%rbp), %xmm0");
+ asm volatile("sha256msg1 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rax), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rbp), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* sha256msg2 xmm2/m128, xmm1 */
+
+ asm volatile("sha256msg2 %xmm1, %xmm0");
+ asm volatile("sha256msg2 %xmm7, %xmm2");
+ asm volatile("sha256msg2 %xmm8, %xmm0");
+ asm volatile("sha256msg2 %xmm7, %xmm8");
+ asm volatile("sha256msg2 %xmm15, %xmm8");
+ asm volatile("sha256msg2 (%rax), %xmm0");
+ asm volatile("sha256msg2 (%r8), %xmm0");
+ asm volatile("sha256msg2 (0x12345678), %xmm0");
+ asm volatile("sha256msg2 (%rax), %xmm3");
+ asm volatile("sha256msg2 (%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(,%rax,1), %xmm0");
+ asm volatile("sha256msg2 (%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg2 (%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg2 0x12(%rax), %xmm0");
+ asm volatile("sha256msg2 0x12(%rbp), %xmm0");
+ asm volatile("sha256msg2 0x12(%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%rbp,%rax,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rax), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rbp), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rcx,%rax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rbp,%rax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rax,%rcx,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15");
+
+ /* clflushopt m8 */
+
+ asm volatile("clflushopt (%rax)");
+ asm volatile("clflushopt (%r8)");
+ asm volatile("clflushopt (0x12345678)");
+ asm volatile("clflushopt 0x12345678(%rax,%rcx,8)");
+ asm volatile("clflushopt 0x12345678(%r8,%rcx,8)");
+ /* Also check instructions in the same group encoding as clflushopt */
+ asm volatile("clflush (%rax)");
+ asm volatile("clflush (%r8)");
+ asm volatile("sfence");
+
+ /* clwb m8 */
+
+ asm volatile("clwb (%rax)");
+ asm volatile("clwb (%r8)");
+ asm volatile("clwb (0x12345678)");
+ asm volatile("clwb 0x12345678(%rax,%rcx,8)");
+ asm volatile("clwb 0x12345678(%r8,%rcx,8)");
+ /* Also check instructions in the same group encoding as clwb */
+ asm volatile("xsaveopt (%rax)");
+ asm volatile("xsaveopt (%r8)");
+ asm volatile("mfence");
+
+ /* xsavec mem */
+
+ asm volatile("xsavec (%rax)");
+ asm volatile("xsavec (%r8)");
+ asm volatile("xsavec (0x12345678)");
+ asm volatile("xsavec 0x12345678(%rax,%rcx,8)");
+ asm volatile("xsavec 0x12345678(%r8,%rcx,8)");
+
+ /* xsaves mem */
+
+ asm volatile("xsaves (%rax)");
+ asm volatile("xsaves (%r8)");
+ asm volatile("xsaves (0x12345678)");
+ asm volatile("xsaves 0x12345678(%rax,%rcx,8)");
+ asm volatile("xsaves 0x12345678(%r8,%rcx,8)");
+
+ /* xrstors mem */
+
+ asm volatile("xrstors (%rax)");
+ asm volatile("xrstors (%r8)");
+ asm volatile("xrstors (0x12345678)");
+ asm volatile("xrstors 0x12345678(%rax,%rcx,8)");
+ asm volatile("xrstors 0x12345678(%r8,%rcx,8)");
+
+#else /* #ifdef __x86_64__ */
+
+ /* bndmk m32, bnd */
+
+ asm volatile("bndmk (%eax), %bnd0");
+ asm volatile("bndmk (0x12345678), %bnd0");
+ asm volatile("bndmk (%eax), %bnd3");
+ asm volatile("bndmk (%ecx,%eax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndmk (%eax,%ecx,1), %bnd0");
+ asm volatile("bndmk (%eax,%ecx,8), %bnd0");
+ asm volatile("bndmk 0x12(%eax), %bnd0");
+ asm volatile("bndmk 0x12(%ebp), %bnd0");
+ asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0");
+ asm volatile("bndmk 0x12345678(%eax), %bnd0");
+ asm volatile("bndmk 0x12345678(%ebp), %bnd0");
+ asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0");
+ asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0");
+
+ /* bndcl r/m32, bnd */
+
+ asm volatile("bndcl (%eax), %bnd0");
+ asm volatile("bndcl (0x12345678), %bnd0");
+ asm volatile("bndcl (%eax), %bnd3");
+ asm volatile("bndcl (%ecx,%eax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndcl (%eax,%ecx,1), %bnd0");
+ asm volatile("bndcl (%eax,%ecx,8), %bnd0");
+ asm volatile("bndcl 0x12(%eax), %bnd0");
+ asm volatile("bndcl 0x12(%ebp), %bnd0");
+ asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcl 0x12345678(%eax), %bnd0");
+ asm volatile("bndcl 0x12345678(%ebp), %bnd0");
+ asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcl %eax, %bnd0");
+
+ /* bndcu r/m32, bnd */
+
+ asm volatile("bndcu (%eax), %bnd0");
+ asm volatile("bndcu (0x12345678), %bnd0");
+ asm volatile("bndcu (%eax), %bnd3");
+ asm volatile("bndcu (%ecx,%eax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndcu (%eax,%ecx,1), %bnd0");
+ asm volatile("bndcu (%eax,%ecx,8), %bnd0");
+ asm volatile("bndcu 0x12(%eax), %bnd0");
+ asm volatile("bndcu 0x12(%ebp), %bnd0");
+ asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcu 0x12345678(%eax), %bnd0");
+ asm volatile("bndcu 0x12345678(%ebp), %bnd0");
+ asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcu %eax, %bnd0");
+
+ /* bndcn r/m32, bnd */
+
+ asm volatile("bndcn (%eax), %bnd0");
+ asm volatile("bndcn (0x12345678), %bnd0");
+ asm volatile("bndcn (%eax), %bnd3");
+ asm volatile("bndcn (%ecx,%eax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndcn (%eax,%ecx,1), %bnd0");
+ asm volatile("bndcn (%eax,%ecx,8), %bnd0");
+ asm volatile("bndcn 0x12(%eax), %bnd0");
+ asm volatile("bndcn 0x12(%ebp), %bnd0");
+ asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcn 0x12345678(%eax), %bnd0");
+ asm volatile("bndcn 0x12345678(%ebp), %bnd0");
+ asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0");
+ asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0");
+ asm volatile("bndcn %eax, %bnd0");
+
+ /* bndmov m64, bnd */
+
+ asm volatile("bndmov (%eax), %bnd0");
+ asm volatile("bndmov (0x12345678), %bnd0");
+ asm volatile("bndmov (%eax), %bnd3");
+ asm volatile("bndmov (%ecx,%eax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndmov (%eax,%ecx,1), %bnd0");
+ asm volatile("bndmov (%eax,%ecx,8), %bnd0");
+ asm volatile("bndmov 0x12(%eax), %bnd0");
+ asm volatile("bndmov 0x12(%ebp), %bnd0");
+ asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0");
+ asm volatile("bndmov 0x12345678(%eax), %bnd0");
+ asm volatile("bndmov 0x12345678(%ebp), %bnd0");
+ asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0");
+ asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0");
+
+ /* bndmov bnd, m64 */
+
+ asm volatile("bndmov %bnd0, (%eax)");
+ asm volatile("bndmov %bnd0, (0x12345678)");
+ asm volatile("bndmov %bnd3, (%eax)");
+ asm volatile("bndmov %bnd0, (%ecx,%eax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)");
+ asm volatile("bndmov %bnd0, (%eax,%ecx,1)");
+ asm volatile("bndmov %bnd0, (%eax,%ecx,8)");
+ asm volatile("bndmov %bnd0, 0x12(%eax)");
+ asm volatile("bndmov %bnd0, 0x12(%ebp)");
+ asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)");
+ asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)");
+ asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)");
+ asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)");
+ asm volatile("bndmov %bnd0, 0x12345678(%eax)");
+ asm volatile("bndmov %bnd0, 0x12345678(%ebp)");
+ asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)");
+ asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)");
+
+ /* bndmov bnd2, bnd1 */
+
+ asm volatile("bndmov %bnd0, %bnd1");
+ asm volatile("bndmov %bnd1, %bnd0");
+
+ /* bndldx mib, bnd */
+
+ asm volatile("bndldx (%eax), %bnd0");
+ asm volatile("bndldx (0x12345678), %bnd0");
+ asm volatile("bndldx (%eax), %bnd3");
+ asm volatile("bndldx (%ecx,%eax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(,%eax,1), %bnd0");
+ asm volatile("bndldx (%eax,%ecx,1), %bnd0");
+ asm volatile("bndldx 0x12(%eax), %bnd0");
+ asm volatile("bndldx 0x12(%ebp), %bnd0");
+ asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0");
+ asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0");
+ asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%eax), %bnd0");
+ asm volatile("bndldx 0x12345678(%ebp), %bnd0");
+ asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0");
+ asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0");
+
+ /* bndstx bnd, mib */
+
+ asm volatile("bndstx %bnd0, (%eax)");
+ asm volatile("bndstx %bnd0, (0x12345678)");
+ asm volatile("bndstx %bnd3, (%eax)");
+ asm volatile("bndstx %bnd0, (%ecx,%eax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)");
+ asm volatile("bndstx %bnd0, (%eax,%ecx,1)");
+ asm volatile("bndstx %bnd0, 0x12(%eax)");
+ asm volatile("bndstx %bnd0, 0x12(%ebp)");
+ asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)");
+ asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)");
+ asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%eax)");
+ asm volatile("bndstx %bnd0, 0x12345678(%ebp)");
+ asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)");
+ asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)");
+
+ /* bnd prefix on call, ret, jmp and all jcc */
+
+ asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */
+ asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
+ asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
+ asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
+ asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
+ asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
+ asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */
+
+ /* sha1rnds4 imm8, xmm2/m128, xmm1 */
+
+ asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
+ asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
+ asm volatile("sha1rnds4 $0x91, (%eax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%eax), %xmm3");
+ asm volatile("sha1rnds4 $0x91, (%ecx,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%eax,%ecx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, (%eax,%ecx,8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%eax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%ebp), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%eax), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* sha1nexte xmm2/m128, xmm1 */
+
+ asm volatile("sha1nexte %xmm1, %xmm0");
+ asm volatile("sha1nexte %xmm7, %xmm2");
+ asm volatile("sha1nexte (%eax), %xmm0");
+ asm volatile("sha1nexte (0x12345678), %xmm0");
+ asm volatile("sha1nexte (%eax), %xmm3");
+ asm volatile("sha1nexte (%ecx,%eax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha1nexte (%eax,%ecx,1), %xmm0");
+ asm volatile("sha1nexte (%eax,%ecx,8), %xmm0");
+ asm volatile("sha1nexte 0x12(%eax), %xmm0");
+ asm volatile("sha1nexte 0x12(%ebp), %xmm0");
+ asm volatile("sha1nexte 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1nexte 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%eax), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%ebp), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1nexte 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* sha1msg1 xmm2/m128, xmm1 */
+
+ asm volatile("sha1msg1 %xmm1, %xmm0");
+ asm volatile("sha1msg1 %xmm7, %xmm2");
+ asm volatile("sha1msg1 (%eax), %xmm0");
+ asm volatile("sha1msg1 (0x12345678), %xmm0");
+ asm volatile("sha1msg1 (%eax), %xmm3");
+ asm volatile("sha1msg1 (%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha1msg1 (%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg1 (%eax,%ecx,8), %xmm0");
+ asm volatile("sha1msg1 0x12(%eax), %xmm0");
+ asm volatile("sha1msg1 0x12(%ebp), %xmm0");
+ asm volatile("sha1msg1 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg1 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%eax), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%ebp), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg1 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* sha1msg2 xmm2/m128, xmm1 */
+
+ asm volatile("sha1msg2 %xmm1, %xmm0");
+ asm volatile("sha1msg2 %xmm7, %xmm2");
+ asm volatile("sha1msg2 (%eax), %xmm0");
+ asm volatile("sha1msg2 (0x12345678), %xmm0");
+ asm volatile("sha1msg2 (%eax), %xmm3");
+ asm volatile("sha1msg2 (%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha1msg2 (%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg2 (%eax,%ecx,8), %xmm0");
+ asm volatile("sha1msg2 0x12(%eax), %xmm0");
+ asm volatile("sha1msg2 0x12(%ebp), %xmm0");
+ asm volatile("sha1msg2 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg2 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%eax), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%ebp), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha1msg2 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
+ /* Note sha256rnds2 has an implicit operand 'xmm0' */
+
+ asm volatile("sha256rnds2 %xmm4, %xmm1");
+ asm volatile("sha256rnds2 %xmm7, %xmm2");
+ asm volatile("sha256rnds2 (%eax), %xmm1");
+ asm volatile("sha256rnds2 (0x12345678), %xmm1");
+ asm volatile("sha256rnds2 (%eax), %xmm3");
+ asm volatile("sha256rnds2 (%ecx,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 (%eax,%ecx,1), %xmm1");
+ asm volatile("sha256rnds2 (%eax,%ecx,8), %xmm1");
+ asm volatile("sha256rnds2 0x12(%eax), %xmm1");
+ asm volatile("sha256rnds2 0x12(%ebp), %xmm1");
+ asm volatile("sha256rnds2 0x12(%ecx,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%ebp,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%eax,%ecx,1), %xmm1");
+ asm volatile("sha256rnds2 0x12(%eax,%ecx,8), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%eax), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%ebp), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%ecx,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%ebp,%eax,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%eax,%ecx,1), %xmm1");
+ asm volatile("sha256rnds2 0x12345678(%eax,%ecx,8), %xmm1");
+
+ /* sha256msg1 xmm2/m128, xmm1 */
+
+ asm volatile("sha256msg1 %xmm1, %xmm0");
+ asm volatile("sha256msg1 %xmm7, %xmm2");
+ asm volatile("sha256msg1 (%eax), %xmm0");
+ asm volatile("sha256msg1 (0x12345678), %xmm0");
+ asm volatile("sha256msg1 (%eax), %xmm3");
+ asm volatile("sha256msg1 (%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha256msg1 (%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg1 (%eax,%ecx,8), %xmm0");
+ asm volatile("sha256msg1 0x12(%eax), %xmm0");
+ asm volatile("sha256msg1 0x12(%ebp), %xmm0");
+ asm volatile("sha256msg1 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg1 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%eax), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%ebp), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg1 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* sha256msg2 xmm2/m128, xmm1 */
+
+ asm volatile("sha256msg2 %xmm1, %xmm0");
+ asm volatile("sha256msg2 %xmm7, %xmm2");
+ asm volatile("sha256msg2 (%eax), %xmm0");
+ asm volatile("sha256msg2 (0x12345678), %xmm0");
+ asm volatile("sha256msg2 (%eax), %xmm3");
+ asm volatile("sha256msg2 (%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(,%eax,1), %xmm0");
+ asm volatile("sha256msg2 (%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg2 (%eax,%ecx,8), %xmm0");
+ asm volatile("sha256msg2 0x12(%eax), %xmm0");
+ asm volatile("sha256msg2 0x12(%ebp), %xmm0");
+ asm volatile("sha256msg2 0x12(%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%ebp,%eax,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg2 0x12(%eax,%ecx,8), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%eax), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%ebp), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%ecx,%eax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%ebp,%eax,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0");
+ asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0");
+
+ /* clflushopt m8 */
+
+ asm volatile("clflushopt (%eax)");
+ asm volatile("clflushopt (0x12345678)");
+ asm volatile("clflushopt 0x12345678(%eax,%ecx,8)");
+ /* Also check instructions in the same group encoding as clflushopt */
+ asm volatile("clflush (%eax)");
+ asm volatile("sfence");
+
+ /* clwb m8 */
+
+ asm volatile("clwb (%eax)");
+ asm volatile("clwb (0x12345678)");
+ asm volatile("clwb 0x12345678(%eax,%ecx,8)");
+ /* Also check instructions in the same group encoding as clwb */
+ asm volatile("xsaveopt (%eax)");
+ asm volatile("mfence");
+
+ /* xsavec mem */
+
+ asm volatile("xsavec (%eax)");
+ asm volatile("xsavec (0x12345678)");
+ asm volatile("xsavec 0x12345678(%eax,%ecx,8)");
+
+ /* xsaves mem */
+
+ asm volatile("xsaves (%eax)");
+ asm volatile("xsaves (0x12345678)");
+ asm volatile("xsaves 0x12345678(%eax,%ecx,8)");
+
+ /* xrstors mem */
+
+ asm volatile("xrstors (%eax)");
+ asm volatile("xrstors (0x12345678)");
+ asm volatile("xrstors 0x12345678(%eax,%ecx,8)");
+
+#endif /* #ifndef __x86_64__ */
+
+ /* pcommit */
+
+ asm volatile("pcommit");
+
+ /* Following line is a marker for the awk script - do not change */
+ asm volatile("rdtsc"); /* Stop here */
+
+ return 0;
+}
diff --git a/tools/perf/arch/x86/tests/insn-x86.c b/tools/perf/arch/x86/tests/insn-x86.c
new file mode 100644
index 000000000000..b6115dfd28f0
--- /dev/null
+++ b/tools/perf/arch/x86/tests/insn-x86.c
@@ -0,0 +1,185 @@
+#include <linux/types.h>
+
+#include "debug.h"
+#include "tests/tests.h"
+#include "arch-tests.h"
+
+#include "intel-pt-decoder/insn.h"
+#include "intel-pt-decoder/intel-pt-insn-decoder.h"
+
+struct test_data {
+ u8 data[MAX_INSN_SIZE];
+ int expected_length;
+ int expected_rel;
+ const char *expected_op_str;
+ const char *expected_branch_str;
+ const char *asm_rep;
+};
+
+struct test_data test_data_32[] = {
+#include "insn-x86-dat-32.c"
+ {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
+ {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
+ {{0}, 0, 0, NULL, NULL, NULL},
+};
+
+struct test_data test_data_64[] = {
+#include "insn-x86-dat-64.c"
+ {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
+ {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
+ {{0}, 0, 0, NULL, NULL, NULL},
+};
+
+static int get_op(const char *op_str)
+{
+ struct val_data {
+ const char *name;
+ int val;
+ } vals[] = {
+ {"other", INTEL_PT_OP_OTHER},
+ {"call", INTEL_PT_OP_CALL},
+ {"ret", INTEL_PT_OP_RET},
+ {"jcc", INTEL_PT_OP_JCC},
+ {"jmp", INTEL_PT_OP_JMP},
+ {"loop", INTEL_PT_OP_LOOP},
+ {"iret", INTEL_PT_OP_IRET},
+ {"int", INTEL_PT_OP_INT},
+ {"syscall", INTEL_PT_OP_SYSCALL},
+ {"sysret", INTEL_PT_OP_SYSRET},
+ {NULL, 0},
+ };
+ struct val_data *val;
+
+ if (!op_str || !strlen(op_str))
+ return 0;
+
+ for (val = vals; val->name; val++) {
+ if (!strcmp(val->name, op_str))
+ return val->val;
+ }
+
+ pr_debug("Failed to get op\n");
+
+ return -1;
+}
+
+static int get_branch(const char *branch_str)
+{
+ struct val_data {
+ const char *name;
+ int val;
+ } vals[] = {
+ {"no_branch", INTEL_PT_BR_NO_BRANCH},
+ {"indirect", INTEL_PT_BR_INDIRECT},
+ {"conditional", INTEL_PT_BR_CONDITIONAL},
+ {"unconditional", INTEL_PT_BR_UNCONDITIONAL},
+ {NULL, 0},
+ };
+ struct val_data *val;
+
+ if (!branch_str || !strlen(branch_str))
+ return 0;
+
+ for (val = vals; val->name; val++) {
+ if (!strcmp(val->name, branch_str))
+ return val->val;
+ }
+
+ pr_debug("Failed to get branch\n");
+
+ return -1;
+}
+
+static int test_data_item(struct test_data *dat, int x86_64)
+{
+ struct intel_pt_insn intel_pt_insn;
+ struct insn insn;
+ int op, branch;
+
+ insn_init(&insn, dat->data, MAX_INSN_SIZE, x86_64);
+ insn_get_length(&insn);
+
+ if (!insn_complete(&insn)) {
+ pr_debug("Failed to decode: %s\n", dat->asm_rep);
+ return -1;
+ }
+
+ if (insn.length != dat->expected_length) {
+ pr_debug("Failed to decode length (%d vs expected %d): %s\n",
+ insn.length, dat->expected_length, dat->asm_rep);
+ return -1;
+ }
+
+ op = get_op(dat->expected_op_str);
+ branch = get_branch(dat->expected_branch_str);
+
+ if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) {
+ pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep);
+ return -1;
+ }
+
+ if ((int)intel_pt_insn.op != op) {
+ pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n",
+ intel_pt_insn.op, op, dat->asm_rep);
+ return -1;
+ }
+
+ if ((int)intel_pt_insn.branch != branch) {
+ pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n",
+ intel_pt_insn.branch, branch, dat->asm_rep);
+ return -1;
+ }
+
+ if (intel_pt_insn.rel != dat->expected_rel) {
+ pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n",
+ intel_pt_insn.rel, dat->expected_rel, dat->asm_rep);
+ return -1;
+ }
+
+ pr_debug("Decoded ok: %s\n", dat->asm_rep);
+
+ return 0;
+}
+
+static int test_data_set(struct test_data *dat_set, int x86_64)
+{
+ struct test_data *dat;
+ int ret = 0;
+
+ for (dat = dat_set; dat->expected_length; dat++) {
+ if (test_data_item(dat, x86_64))
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * test__insn_x86 - test x86 instruction decoder - new instructions.
+ *
+ * This function implements a test that decodes a selection of instructions and
+ * checks the results. The Intel PT function that further categorizes
+ * instructions (i.e. intel_pt_get_insn()) is also checked.
+ *
+ * The instructions are originally in insn-x86-dat-src.c which has been
+ * processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce
+ * insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program.
+ * i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the
+ * gen-insn-x86-dat.sh script, make perf, and then run the test.
+ *
+ * If the test passes %0 is returned, otherwise %-1 is returned. Use the
+ * verbose (-v) option to see all the instructions and whether or not they
+ * decoded successfuly.
+ */
+int test__insn_x86(void)
+{
+ int ret = 0;
+
+ if (test_data_set(test_data_32, 0))
+ ret = -1;
+
+ if (test_data_set(test_data_64, 1))
+ ret = -1;
+
+ return ret;
+}
diff --git a/tools/perf/arch/x86/tests/perf-time-to-tsc.c b/tools/perf/arch/x86/tests/perf-time-to-tsc.c
new file mode 100644
index 000000000000..658cd200af74
--- /dev/null
+++ b/tools/perf/arch/x86/tests/perf-time-to-tsc.c
@@ -0,0 +1,164 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <linux/types.h>
+#include <sys/prctl.h>
+
+#include "parse-events.h"
+#include "evlist.h"
+#include "evsel.h"
+#include "thread_map.h"
+#include "cpumap.h"
+#include "tsc.h"
+#include "tests/tests.h"
+
+#include "arch-tests.h"
+
+#define CHECK__(x) { \
+ while ((x) < 0) { \
+ pr_debug(#x " failed!\n"); \
+ goto out_err; \
+ } \
+}
+
+#define CHECK_NOT_NULL__(x) { \
+ while ((x) == NULL) { \
+ pr_debug(#x " failed!\n"); \
+ goto out_err; \
+ } \
+}
+
+/**
+ * test__perf_time_to_tsc - test converting perf time to TSC.
+ *
+ * This function implements a test that checks that the conversion of perf time
+ * to and from TSC is consistent with the order of events. If the test passes
+ * %0 is returned, otherwise %-1 is returned. If TSC conversion is not
+ * supported then then the test passes but " (not supported)" is printed.
+ */
+int test__perf_time_to_tsc(void)
+{
+ struct record_opts opts = {
+ .mmap_pages = UINT_MAX,
+ .user_freq = UINT_MAX,
+ .user_interval = ULLONG_MAX,
+ .freq = 4000,
+ .target = {
+ .uses_mmap = true,
+ },
+ .sample_time = true,
+ };
+ struct thread_map *threads = NULL;
+ struct cpu_map *cpus = NULL;
+ struct perf_evlist *evlist = NULL;
+ struct perf_evsel *evsel = NULL;
+ int err = -1, ret, i;
+ const char *comm1, *comm2;
+ struct perf_tsc_conversion tc;
+ struct perf_event_mmap_page *pc;
+ union perf_event *event;
+ u64 test_tsc, comm1_tsc, comm2_tsc;
+ u64 test_time, comm1_time = 0, comm2_time = 0;
+
+ threads = thread_map__new(-1, getpid(), UINT_MAX);
+ CHECK_NOT_NULL__(threads);
+
+ cpus = cpu_map__new(NULL);
+ CHECK_NOT_NULL__(cpus);
+
+ evlist = perf_evlist__new();
+ CHECK_NOT_NULL__(evlist);
+
+ perf_evlist__set_maps(evlist, cpus, threads);
+
+ CHECK__(parse_events(evlist, "cycles:u", NULL));
+
+ perf_evlist__config(evlist, &opts);
+
+ evsel = perf_evlist__first(evlist);
+
+ evsel->attr.comm = 1;
+ evsel->attr.disabled = 1;
+ evsel->attr.enable_on_exec = 0;
+
+ CHECK__(perf_evlist__open(evlist));
+
+ CHECK__(perf_evlist__mmap(evlist, UINT_MAX, false));
+
+ pc = evlist->mmap[0].base;
+ ret = perf_read_tsc_conversion(pc, &tc);
+ if (ret) {
+ if (ret == -EOPNOTSUPP) {
+ fprintf(stderr, " (not supported)");
+ return 0;
+ }
+ goto out_err;
+ }
+
+ perf_evlist__enable(evlist);
+
+ comm1 = "Test COMM 1";
+ CHECK__(prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0));
+
+ test_tsc = rdtsc();
+
+ comm2 = "Test COMM 2";
+ CHECK__(prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0));
+
+ perf_evlist__disable(evlist);
+
+ for (i = 0; i < evlist->nr_mmaps; i++) {
+ while ((event = perf_evlist__mmap_read(evlist, i)) != NULL) {
+ struct perf_sample sample;
+
+ if (event->header.type != PERF_RECORD_COMM ||
+ (pid_t)event->comm.pid != getpid() ||
+ (pid_t)event->comm.tid != getpid())
+ goto next_event;
+
+ if (strcmp(event->comm.comm, comm1) == 0) {
+ CHECK__(perf_evsel__parse_sample(evsel, event,
+ &sample));
+ comm1_time = sample.time;
+ }
+ if (strcmp(event->comm.comm, comm2) == 0) {
+ CHECK__(perf_evsel__parse_sample(evsel, event,
+ &sample));
+ comm2_time = sample.time;
+ }
+next_event:
+ perf_evlist__mmap_consume(evlist, i);
+ }
+ }
+
+ if (!comm1_time || !comm2_time)
+ goto out_err;
+
+ test_time = tsc_to_perf_time(test_tsc, &tc);
+ comm1_tsc = perf_time_to_tsc(comm1_time, &tc);
+ comm2_tsc = perf_time_to_tsc(comm2_time, &tc);
+
+ pr_debug("1st event perf time %"PRIu64" tsc %"PRIu64"\n",
+ comm1_time, comm1_tsc);
+ pr_debug("rdtsc time %"PRIu64" tsc %"PRIu64"\n",
+ test_time, test_tsc);
+ pr_debug("2nd event perf time %"PRIu64" tsc %"PRIu64"\n",
+ comm2_time, comm2_tsc);
+
+ if (test_time <= comm1_time ||
+ test_time >= comm2_time)
+ goto out_err;
+
+ if (test_tsc <= comm1_tsc ||
+ test_tsc >= comm2_tsc)
+ goto out_err;
+
+ err = 0;
+
+out_err:
+ if (evlist) {
+ perf_evlist__disable(evlist);
+ perf_evlist__delete(evlist);
+ }
+
+ return err;
+}
diff --git a/tools/perf/arch/x86/tests/rdpmc.c b/tools/perf/arch/x86/tests/rdpmc.c
new file mode 100644
index 000000000000..e7688214c7cf
--- /dev/null
+++ b/tools/perf/arch/x86/tests/rdpmc.c
@@ -0,0 +1,174 @@
+#include <unistd.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include <linux/types.h>
+#include "perf.h"
+#include "debug.h"
+#include "tests/tests.h"
+#include "cloexec.h"
+#include "arch-tests.h"
+
+static u64 rdpmc(unsigned int counter)
+{
+ unsigned int low, high;
+
+ asm volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (counter));
+
+ return low | ((u64)high) << 32;
+}
+
+static u64 rdtsc(void)
+{
+ unsigned int low, high;
+
+ asm volatile("rdtsc" : "=a" (low), "=d" (high));
+
+ return low | ((u64)high) << 32;
+}
+
+static u64 mmap_read_self(void *addr)
+{
+ struct perf_event_mmap_page *pc = addr;
+ u32 seq, idx, time_mult = 0, time_shift = 0;
+ u64 count, cyc = 0, time_offset = 0, enabled, running, delta;
+
+ do {
+ seq = pc->lock;
+ barrier();
+
+ enabled = pc->time_enabled;
+ running = pc->time_running;
+
+ if (enabled != running) {
+ cyc = rdtsc();
+ time_mult = pc->time_mult;
+ time_shift = pc->time_shift;
+ time_offset = pc->time_offset;
+ }
+
+ idx = pc->index;
+ count = pc->offset;
+ if (idx)
+ count += rdpmc(idx - 1);
+
+ barrier();
+ } while (pc->lock != seq);
+
+ if (enabled != running) {
+ u64 quot, rem;
+
+ quot = (cyc >> time_shift);
+ rem = cyc & ((1 << time_shift) - 1);
+ delta = time_offset + quot * time_mult +
+ ((rem * time_mult) >> time_shift);
+
+ enabled += delta;
+ if (idx)
+ running += delta;
+
+ quot = count / running;
+ rem = count % running;
+ count = quot * enabled + (rem * enabled) / running;
+ }
+
+ return count;
+}
+
+/*
+ * If the RDPMC instruction faults then signal this back to the test parent task:
+ */
+static void segfault_handler(int sig __maybe_unused,
+ siginfo_t *info __maybe_unused,
+ void *uc __maybe_unused)
+{
+ exit(-1);
+}
+
+static int __test__rdpmc(void)
+{
+ volatile int tmp = 0;
+ u64 i, loops = 1000;
+ int n;
+ int fd;
+ void *addr;
+ struct perf_event_attr attr = {
+ .type = PERF_TYPE_HARDWARE,
+ .config = PERF_COUNT_HW_INSTRUCTIONS,
+ .exclude_kernel = 1,
+ };
+ u64 delta_sum = 0;
+ struct sigaction sa;
+ char sbuf[STRERR_BUFSIZE];
+
+ sigfillset(&sa.sa_mask);
+ sa.sa_sigaction = segfault_handler;
+ sigaction(SIGSEGV, &sa, NULL);
+
+ fd = sys_perf_event_open(&attr, 0, -1, -1,
+ perf_event_open_cloexec_flag());
+ if (fd < 0) {
+ pr_err("Error: sys_perf_event_open() syscall returned "
+ "with %d (%s)\n", fd,
+ strerror_r(errno, sbuf, sizeof(sbuf)));
+ return -1;
+ }
+
+ addr = mmap(NULL, page_size, PROT_READ, MAP_SHARED, fd, 0);
+ if (addr == (void *)(-1)) {
+ pr_err("Error: mmap() syscall returned with (%s)\n",
+ strerror_r(errno, sbuf, sizeof(sbuf)));
+ goto out_close;
+ }
+
+ for (n = 0; n < 6; n++) {
+ u64 stamp, now, delta;
+
+ stamp = mmap_read_self(addr);
+
+ for (i = 0; i < loops; i++)
+ tmp++;
+
+ now = mmap_read_self(addr);
+ loops *= 10;
+
+ delta = now - stamp;
+ pr_debug("%14d: %14Lu\n", n, (long long)delta);
+
+ delta_sum += delta;
+ }
+
+ munmap(addr, page_size);
+ pr_debug(" ");
+out_close:
+ close(fd);
+
+ if (!delta_sum)
+ return -1;
+
+ return 0;
+}
+
+int test__rdpmc(void)
+{
+ int status = 0;
+ int wret = 0;
+ int ret;
+ int pid;
+
+ pid = fork();
+ if (pid < 0)
+ return -1;
+
+ if (!pid) {
+ ret = __test__rdpmc();
+
+ exit(ret);
+ }
+
+ wret = waitpid(pid, &status, 0);
+ if (wret < 0 || status)
+ return -1;
+
+ return 0;
+}
diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build
index c6f198ae65fb..50de2253cff6 100644
--- a/tools/perf/tests/Build
+++ b/tools/perf/tests/Build
@@ -8,7 +8,6 @@ perf-y += openat-syscall-all-cpus.o
perf-y += openat-syscall-tp-fields.o
perf-y += mmap-basic.o
perf-y += perf-record.o
-perf-y += rdpmc.o
perf-y += evsel-roundtrip-name.o
perf-y += evsel-tp-sched.o
perf-y += fdarray.o
@@ -35,11 +34,6 @@ perf-y += thread-map.o
perf-y += llvm.o
perf-y += topology.o

-perf-$(CONFIG_X86) += perf-time-to-tsc.o
-ifdef CONFIG_AUXTRACE
-perf-$(CONFIG_X86) += insn-x86.o
-endif
-
ifeq ($(ARCH),$(filter $(ARCH),x86 arm arm64))
perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o
endif
diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c
index 2b6c1bf13456..66f72d3d6677 100644
--- a/tools/perf/tests/builtin-test.c
+++ b/tools/perf/tests/builtin-test.c
@@ -41,12 +41,6 @@ static struct test generic_tests[] = {
.desc = "parse events tests",
.func = test__parse_events,
},
-#if defined(__x86_64__) || defined(__i386__)
- {
- .desc = "x86 rdpmc test",
- .func = test__rdpmc,
- },
-#endif
{
.desc = "Validate PERF_RECORD_* events & perf_sample fields",
.func = test__PERF_RECORD,
@@ -107,12 +101,6 @@ static struct test generic_tests[] = {
.desc = "Test software clock events have valid period values",
.func = test__sw_clock_freq,
},
-#if defined(__x86_64__) || defined(__i386__)
- {
- .desc = "Test converting perf time to TSC",
- .func = test__perf_time_to_tsc,
- },
-#endif
{
.desc = "Test object code reading",
.func = test__code_reading,
@@ -129,14 +117,6 @@ static struct test generic_tests[] = {
.desc = "Test parsing with no sample_id_all bit set",
.func = test__parse_no_sample_id_all,
},
-#if defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__)
-#ifdef HAVE_DWARF_UNWIND_SUPPORT
- {
- .desc = "Test dwarf unwind",
- .func = test__dwarf_unwind,
- },
-#endif
-#endif
{
.desc = "Test filtering hist entries",
.func = test__hists_filter,
@@ -181,14 +161,6 @@ static struct test generic_tests[] = {
.desc = "Test LLVM searching and compiling",
.func = test__llvm,
},
-#ifdef HAVE_AUXTRACE_SUPPORT
-#if defined(__x86_64__) || defined(__i386__)
- {
- .desc = "Test x86 instruction decoder - new instructions",
- .func = test__insn_x86,
- },
-#endif
-#endif
{
.desc = "Test topology in session",
.func = test_session_topology,
diff --git a/tools/perf/tests/dwarf-unwind.c b/tools/perf/tests/dwarf-unwind.c
index 40b36c462427..07221793a3ac 100644
--- a/tools/perf/tests/dwarf-unwind.c
+++ b/tools/perf/tests/dwarf-unwind.c
@@ -11,6 +11,10 @@
#include "thread.h"
#include "callchain.h"

+#if defined (__x86_64__) || defined (__i386__)
+#include "arch-tests.h"
+#endif
+
/* For bsearch. We try to unwind functions in shared object. */
#include <stdlib.h>

diff --git a/tools/perf/tests/gen-insn-x86-dat.awk b/tools/perf/tests/gen-insn-x86-dat.awk
deleted file mode 100644
index a21454835cd4..000000000000
--- a/tools/perf/tests/gen-insn-x86-dat.awk
+++ /dev/null
@@ -1,75 +0,0 @@
-#!/bin/awk -f
-# gen-insn-x86-dat.awk: script to convert data for the insn-x86 test
-# Copyright (c) 2015, Intel Corporation.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-
-BEGIN {
- print "/*"
- print " * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk"
- print " * from insn-x86-dat-src.c for inclusion by insn-x86.c"
- print " * Do not change this code."
- print "*/\n"
- op = ""
- branch = ""
- rel = 0
- going = 0
-}
-
-/ Start here / {
- going = 1
-}
-
-/ Stop here / {
- going = 0
-}
-
-/^\s*[0-9a-fA-F]+\:/ {
- if (going) {
- colon_pos = index($0, ":")
- useful_line = substr($0, colon_pos + 1)
- first_pos = match(useful_line, "[0-9a-fA-F]")
- useful_line = substr(useful_line, first_pos)
- gsub("\t", "\\t", useful_line)
- printf "{{"
- len = 0
- for (i = 2; i <= NF; i++) {
- if (match($i, "^[0-9a-fA-F][0-9a-fA-F]$")) {
- printf "0x%s, ", $i
- len += 1
- } else {
- break
- }
- }
- printf "}, %d, %s, \"%s\", \"%s\",", len, rel, op, branch
- printf "\n\"%s\",},\n", useful_line
- op = ""
- branch = ""
- rel = 0
- }
-}
-
-/ Expecting: / {
- expecting_str = " Expecting: "
- expecting_len = length(expecting_str)
- expecting_pos = index($0, expecting_str)
- useful_line = substr($0, expecting_pos + expecting_len)
- for (i = 1; i <= NF; i++) {
- if ($i == "Expecting:") {
- i++
- op = $i
- i++
- branch = $i
- i++
- rel = $i
- break
- }
- }
-}
diff --git a/tools/perf/tests/gen-insn-x86-dat.sh b/tools/perf/tests/gen-insn-x86-dat.sh
deleted file mode 100755
index 2d4ef94cff98..000000000000
--- a/tools/perf/tests/gen-insn-x86-dat.sh
+++ /dev/null
@@ -1,43 +0,0 @@
-#!/bin/sh
-# gen-insn-x86-dat: generate data for the insn-x86 test
-# Copyright (c) 2015, Intel Corporation.
-#
-# This program is free software; you can redistribute it and/or modify it
-# under the terms and conditions of the GNU General Public License,
-# version 2, as published by the Free Software Foundation.
-#
-# This program is distributed in the hope it will be useful, but WITHOUT
-# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-# more details.
-
-set -e
-
-if [ "$(uname -m)" != "x86_64" ]; then
- echo "ERROR: This script only works on x86_64"
- exit 1
-fi
-
-cd $(dirname $0)
-
-trap 'echo "Might need a more recent version of binutils"' EXIT
-
-echo "Compiling insn-x86-dat-src.c to 64-bit object"
-
-gcc -g -c insn-x86-dat-src.c
-
-objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-64.c
-
-rm -f insn-x86-dat-src.o
-
-echo "Compiling insn-x86-dat-src.c to 32-bit object"
-
-gcc -g -c -m32 insn-x86-dat-src.c
-
-objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-32.c
-
-rm -f insn-x86-dat-src.o
-
-trap - EXIT
-
-echo "Done (use git diff to see the changes)"
diff --git a/tools/perf/tests/insn-x86-dat-32.c b/tools/perf/tests/insn-x86-dat-32.c
deleted file mode 100644
index 3b491cfe204e..000000000000
--- a/tools/perf/tests/insn-x86-dat-32.c
+++ /dev/null
@@ -1,658 +0,0 @@
-/*
- * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
- * from insn-x86-dat-src.c for inclusion by insn-x86.c
- * Do not change this code.
-*/
-
-{{0x0f, 0x31, }, 2, 0, "", "",
-"0f 31 \trdtsc ",},
-{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
-"f3 0f 1b 00 \tbndmk (%eax),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
-"f3 0f 1b 18 \tbndmk (%eax),%bnd3",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
-"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
-"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
-"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
-"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
-"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%ebp,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%eax,%ecx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
-"f3 0f 1a 00 \tbndcl (%eax),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1a 05 78 56 34 12 \tbndcl 0x12345678,%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
-"f3 0f 1a 18 \tbndcl (%eax),%bnd3",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
-"f3 0f 1a 04 01 \tbndcl (%ecx,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%eax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
-"f3 0f 1a 04 08 \tbndcl (%eax,%ecx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
-"f3 0f 1a 04 c8 \tbndcl (%eax,%ecx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
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-{{0x0f, 0x38, 0xcb, 0x8c, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c 05 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%ebp,%eax,1),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c 08 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%eax,%ecx,1),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c c8 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%eax,%ecx,8),%xmm1",},
-{{0x0f, 0x38, 0xcc, 0xc1, }, 4, 0, "", "",
-"0f 38 cc c1 \tsha256msg1 %xmm1,%xmm0",},
-{{0x0f, 0x38, 0xcc, 0xd7, }, 4, 0, "", "",
-"0f 38 cc d7 \tsha256msg1 %xmm7,%xmm2",},
-{{0x0f, 0x38, 0xcc, 0x00, }, 4, 0, "", "",
-"0f 38 cc 00 \tsha256msg1 (%eax),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cc 05 78 56 34 12 \tsha256msg1 0x12345678,%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x18, }, 4, 0, "", "",
-"0f 38 cc 18 \tsha256msg1 (%eax),%xmm3",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x01, }, 5, 0, "", "",
-"0f 38 cc 04 01 \tsha256msg1 (%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 04 05 78 56 34 12 \tsha256msg1 0x12345678(,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x08, }, 5, 0, "", "",
-"0f 38 cc 04 08 \tsha256msg1 (%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0xc8, }, 5, 0, "", "",
-"0f 38 cc 04 c8 \tsha256msg1 (%eax,%ecx,8),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x40, 0x12, }, 5, 0, "", "",
-"0f 38 cc 40 12 \tsha256msg1 0x12(%eax),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x45, 0x12, }, 5, 0, "", "",
-"0f 38 cc 45 12 \tsha256msg1 0x12(%ebp),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 01 12 \tsha256msg1 0x12(%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 05 12 \tsha256msg1 0x12(%ebp,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 08 12 \tsha256msg1 0x12(%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
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-{{0x0f, 0x38, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
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-{{0x0f, 0x38, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cc 85 78 56 34 12 \tsha256msg1 0x12345678(%ebp),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 01 78 56 34 12 \tsha256msg1 0x12345678(%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 05 78 56 34 12 \tsha256msg1 0x12345678(%ebp,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 08 78 56 34 12 \tsha256msg1 0x12345678(%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 c8 78 56 34 12 \tsha256msg1 0x12345678(%eax,%ecx,8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0xc1, }, 4, 0, "", "",
-"0f 38 cd c1 \tsha256msg2 %xmm1,%xmm0",},
-{{0x0f, 0x38, 0xcd, 0xd7, }, 4, 0, "", "",
-"0f 38 cd d7 \tsha256msg2 %xmm7,%xmm2",},
-{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "",
-"0f 38 cd 00 \tsha256msg2 (%eax),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cd 05 78 56 34 12 \tsha256msg2 0x12345678,%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "",
-"0f 38 cd 18 \tsha256msg2 (%eax),%xmm3",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "",
-"0f 38 cd 04 01 \tsha256msg2 (%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "",
-"0f 38 cd 04 08 \tsha256msg2 (%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "",
-"0f 38 cd 04 c8 \tsha256msg2 (%eax,%ecx,8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "",
-"0f 38 cd 40 12 \tsha256msg2 0x12(%eax),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "",
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-{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 01 12 \tsha256msg2 0x12(%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 05 12 \tsha256msg2 0x12(%ebp,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 08 12 \tsha256msg2 0x12(%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%eax,%ecx,8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%eax),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%ebp),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%ecx,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%ebp,%eax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%eax,%ecx,8),%xmm0",},
-{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
-"66 0f ae 38 \tclflushopt (%eax)",},
-{{0x66, 0x0f, 0xae, 0x3d, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f ae 3d 78 56 34 12 \tclflushopt 0x12345678",},
-{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%eax,%ecx,8)",},
-{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
-"0f ae 38 \tclflush (%eax)",},
-{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
-"0f ae f8 \tsfence ",},
-{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
-"66 0f ae 30 \tclwb (%eax)",},
-{{0x66, 0x0f, 0xae, 0x35, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f ae 35 78 56 34 12 \tclwb 0x12345678",},
-{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%eax,%ecx,8)",},
-{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
-"0f ae 30 \txsaveopt (%eax)",},
-{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
-"0f ae f0 \tmfence ",},
-{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
-"0f c7 20 \txsavec (%eax)",},
-{{0x0f, 0xc7, 0x25, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f c7 25 78 56 34 12 \txsavec 0x12345678",},
-{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%eax,%ecx,8)",},
-{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
-"0f c7 28 \txsaves (%eax)",},
-{{0x0f, 0xc7, 0x2d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f c7 2d 78 56 34 12 \txsaves 0x12345678",},
-{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%eax,%ecx,8)",},
-{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
-"0f c7 18 \txrstors (%eax)",},
-{{0x0f, 0xc7, 0x1d, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f c7 1d 78 56 34 12 \txrstors 0x12345678",},
-{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%eax,%ecx,8)",},
-{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
-"66 0f ae f8 \tpcommit ",},
diff --git a/tools/perf/tests/insn-x86-dat-64.c b/tools/perf/tests/insn-x86-dat-64.c
deleted file mode 100644
index 4fe7cce179c4..000000000000
--- a/tools/perf/tests/insn-x86-dat-64.c
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk
- * from insn-x86-dat-src.c for inclusion by insn-x86.c
- * Do not change this code.
-*/
-
-{{0x0f, 0x31, }, 2, 0, "", "",
-"0f 31 \trdtsc ",},
-{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
-"f3 0f 1b 00 \tbndmk (%rax),%bnd0",},
-{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
-"f3 41 0f 1b 00 \tbndmk (%r8),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 04 25 78 56 34 12 \tbndmk 0x12345678,%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
-"f3 0f 1b 18 \tbndmk (%rax),%bnd3",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
-"f3 0f 1b 04 01 \tbndmk (%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
-"f3 0f 1b 04 08 \tbndmk (%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
-"f3 0f 1b 04 c8 \tbndmk (%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
-"f3 0f 1b 40 12 \tbndmk 0x12(%rax),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
-"f3 0f 1b 45 12 \tbndmk 0x12(%rbp),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 01 12 \tbndmk 0x12(%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 05 12 \tbndmk 0x12(%rbp,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 08 12 \tbndmk 0x12(%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"f3 0f 1b 44 c8 12 \tbndmk 0x12(%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%rax),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%rbp),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
-"f3 0f 1a 00 \tbndcl (%rax),%bnd0",},
-{{0xf3, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
-"f3 41 0f 1a 00 \tbndcl (%r8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 04 25 78 56 34 12 \tbndcl 0x12345678,%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
-"f3 0f 1a 18 \tbndcl (%rax),%bnd3",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
-"f3 0f 1a 04 01 \tbndcl (%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
-"f3 0f 1a 04 08 \tbndcl (%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
-"f3 0f 1a 04 c8 \tbndcl (%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
-"f3 0f 1a 40 12 \tbndcl 0x12(%rax),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
-"f3 0f 1a 45 12 \tbndcl 0x12(%rbp),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"f3 0f 1a 44 01 12 \tbndcl 0x12(%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"f3 0f 1a 44 05 12 \tbndcl 0x12(%rbp,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"f3 0f 1a 44 08 12 \tbndcl 0x12(%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"f3 0f 1a 44 c8 12 \tbndcl 0x12(%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%rax),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%rbp),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,8),%bnd0",},
-{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
-"f3 0f 1a c0 \tbndcl %rax,%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
-"f2 0f 1a 00 \tbndcu (%rax),%bnd0",},
-{{0xf2, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
-"f2 41 0f 1a 00 \tbndcu (%r8),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 04 25 78 56 34 12 \tbndcu 0x12345678,%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
-"f2 0f 1a 18 \tbndcu (%rax),%bnd3",},
-{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
-"f2 0f 1a 04 01 \tbndcu (%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
-"f2 0f 1a 04 08 \tbndcu (%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
-"f2 0f 1a 04 c8 \tbndcu (%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
-"f2 0f 1a 40 12 \tbndcu 0x12(%rax),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
-"f2 0f 1a 45 12 \tbndcu 0x12(%rbp),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"f2 0f 1a 44 01 12 \tbndcu 0x12(%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"f2 0f 1a 44 05 12 \tbndcu 0x12(%rbp,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"f2 0f 1a 44 08 12 \tbndcu 0x12(%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"f2 0f 1a 44 c8 12 \tbndcu 0x12(%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%rax),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%rbp),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "",
-"f2 0f 1a c0 \tbndcu %rax,%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
-"f2 0f 1b 00 \tbndcn (%rax),%bnd0",},
-{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
-"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
-"f2 0f 1b 18 \tbndcn (%rax),%bnd3",},
-{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
-"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
-"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
-"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
-"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
-"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",},
-{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "",
-"f2 0f 1b c0 \tbndcn %rax,%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
-"66 0f 1a 00 \tbndmov (%rax),%bnd0",},
-{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "",
-"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "",
-"66 0f 1a 18 \tbndmov (%rax),%bnd3",},
-{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "",
-"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "",
-"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "",
-"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "",
-"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "",
-"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",},
-{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
-"66 0f 1b 00 \tbndmov %bnd0,(%rax)",},
-{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "",
-"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",},
-{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",},
-{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "",
-"66 0f 1b 18 \tbndmov %bnd3,(%rax)",},
-{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "",
-"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "",
-"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",},
-{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "",
-"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",},
-{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "",
-"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",},
-{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "",
-"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",},
-{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",},
-{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",},
-{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",},
-{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",},
-{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 84 05 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp,%rax,1)",},
-{{0x66, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 84 08 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,1)",},
-{{0x66, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f 1b 84 c8 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax,%rcx,8)",},
-{{0x66, 0x0f, 0x1a, 0xc8, }, 4, 0, "", "",
-"66 0f 1a c8 \tbndmov %bnd0,%bnd1",},
-{{0x66, 0x0f, 0x1a, 0xc1, }, 4, 0, "", "",
-"66 0f 1a c1 \tbndmov %bnd1,%bnd0",},
-{{0x0f, 0x1a, 0x00, }, 3, 0, "", "",
-"0f 1a 00 \tbndldx (%rax),%bnd0",},
-{{0x41, 0x0f, 0x1a, 0x00, }, 4, 0, "", "",
-"41 0f 1a 00 \tbndldx (%r8),%bnd0",},
-{{0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1a 04 25 78 56 34 12 \tbndldx 0x12345678,%bnd0",},
-{{0x0f, 0x1a, 0x18, }, 3, 0, "", "",
-"0f 1a 18 \tbndldx (%rax),%bnd3",},
-{{0x0f, 0x1a, 0x04, 0x01, }, 4, 0, "", "",
-"0f 1a 04 01 \tbndldx (%rcx,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1a 04 05 78 56 34 12 \tbndldx 0x12345678(,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x04, 0x08, }, 4, 0, "", "",
-"0f 1a 04 08 \tbndldx (%rax,%rcx,1),%bnd0",},
-{{0x0f, 0x1a, 0x40, 0x12, }, 4, 0, "", "",
-"0f 1a 40 12 \tbndldx 0x12(%rax),%bnd0",},
-{{0x0f, 0x1a, 0x45, 0x12, }, 4, 0, "", "",
-"0f 1a 45 12 \tbndldx 0x12(%rbp),%bnd0",},
-{{0x0f, 0x1a, 0x44, 0x01, 0x12, }, 5, 0, "", "",
-"0f 1a 44 01 12 \tbndldx 0x12(%rcx,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x44, 0x05, 0x12, }, 5, 0, "", "",
-"0f 1a 44 05 12 \tbndldx 0x12(%rbp,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x44, 0x08, 0x12, }, 5, 0, "", "",
-"0f 1a 44 08 12 \tbndldx 0x12(%rax,%rcx,1),%bnd0",},
-{{0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f 1a 80 78 56 34 12 \tbndldx 0x12345678(%rax),%bnd0",},
-{{0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f 1a 85 78 56 34 12 \tbndldx 0x12345678(%rbp),%bnd0",},
-{{0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1a 84 01 78 56 34 12 \tbndldx 0x12345678(%rcx,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1a 84 05 78 56 34 12 \tbndldx 0x12345678(%rbp,%rax,1),%bnd0",},
-{{0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1a 84 08 78 56 34 12 \tbndldx 0x12345678(%rax,%rcx,1),%bnd0",},
-{{0x0f, 0x1b, 0x00, }, 3, 0, "", "",
-"0f 1b 00 \tbndstx %bnd0,(%rax)",},
-{{0x41, 0x0f, 0x1b, 0x00, }, 4, 0, "", "",
-"41 0f 1b 00 \tbndstx %bnd0,(%r8)",},
-{{0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1b 04 25 78 56 34 12 \tbndstx %bnd0,0x12345678",},
-{{0x0f, 0x1b, 0x18, }, 3, 0, "", "",
-"0f 1b 18 \tbndstx %bnd3,(%rax)",},
-{{0x0f, 0x1b, 0x04, 0x01, }, 4, 0, "", "",
-"0f 1b 04 01 \tbndstx %bnd0,(%rcx,%rax,1)",},
-{{0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1b 04 05 78 56 34 12 \tbndstx %bnd0,0x12345678(,%rax,1)",},
-{{0x0f, 0x1b, 0x04, 0x08, }, 4, 0, "", "",
-"0f 1b 04 08 \tbndstx %bnd0,(%rax,%rcx,1)",},
-{{0x0f, 0x1b, 0x40, 0x12, }, 4, 0, "", "",
-"0f 1b 40 12 \tbndstx %bnd0,0x12(%rax)",},
-{{0x0f, 0x1b, 0x45, 0x12, }, 4, 0, "", "",
-"0f 1b 45 12 \tbndstx %bnd0,0x12(%rbp)",},
-{{0x0f, 0x1b, 0x44, 0x01, 0x12, }, 5, 0, "", "",
-"0f 1b 44 01 12 \tbndstx %bnd0,0x12(%rcx,%rax,1)",},
-{{0x0f, 0x1b, 0x44, 0x05, 0x12, }, 5, 0, "", "",
-"0f 1b 44 05 12 \tbndstx %bnd0,0x12(%rbp,%rax,1)",},
-{{0x0f, 0x1b, 0x44, 0x08, 0x12, }, 5, 0, "", "",
-"0f 1b 44 08 12 \tbndstx %bnd0,0x12(%rax,%rcx,1)",},
-{{0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f 1b 80 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax)",},
-{{0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 7, 0, "", "",
-"0f 1b 85 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp)",},
-{{0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1b 84 01 78 56 34 12 \tbndstx %bnd0,0x12345678(%rcx,%rax,1)",},
-{{0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1b 84 05 78 56 34 12 \tbndstx %bnd0,0x12345678(%rbp,%rax,1)",},
-{{0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 1b 84 08 78 56 34 12 \tbndstx %bnd0,0x12345678(%rax,%rcx,1)",},
-{{0xf2, 0xe8, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "call", "unconditional",
-"f2 e8 00 00 00 00 \tbnd callq 3f6 <main+0x3f6>",},
-{{0x67, 0xf2, 0xff, 0x10, }, 4, 0, "call", "indirect",
-"67 f2 ff 10 \tbnd callq *(%eax)",},
-{{0xf2, 0xc3, }, 2, 0, "ret", "indirect",
-"f2 c3 \tbnd retq ",},
-{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
-"f2 e9 00 00 00 00 \tbnd jmpq 402 <main+0x402>",},
-{{0xf2, 0xe9, 0x00, 0x00, 0x00, 0x00, }, 6, 0, "jmp", "unconditional",
-"f2 e9 00 00 00 00 \tbnd jmpq 408 <main+0x408>",},
-{{0x67, 0xf2, 0xff, 0x21, }, 4, 0, "jmp", "indirect",
-"67 f2 ff 21 \tbnd jmpq *(%ecx)",},
-{{0xf2, 0x0f, 0x85, 0x00, 0x00, 0x00, 0x00, }, 7, 0, "jcc", "conditional",
-"f2 0f 85 00 00 00 00 \tbnd jne 413 <main+0x413>",},
-{{0x0f, 0x3a, 0xcc, 0xc1, 0x00, }, 5, 0, "", "",
-"0f 3a cc c1 00 \tsha1rnds4 $0x0,%xmm1,%xmm0",},
-{{0x0f, 0x3a, 0xcc, 0xd7, 0x91, }, 5, 0, "", "",
-"0f 3a cc d7 91 \tsha1rnds4 $0x91,%xmm7,%xmm2",},
-{{0x41, 0x0f, 0x3a, 0xcc, 0xc0, 0x91, }, 6, 0, "", "",
-"41 0f 3a cc c0 91 \tsha1rnds4 $0x91,%xmm8,%xmm0",},
-{{0x44, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
-"44 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm7,%xmm8",},
-{{0x45, 0x0f, 0x3a, 0xcc, 0xc7, 0x91, }, 6, 0, "", "",
-"45 0f 3a cc c7 91 \tsha1rnds4 $0x91,%xmm15,%xmm8",},
-{{0x0f, 0x3a, 0xcc, 0x00, 0x91, }, 5, 0, "", "",
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-"0f 38 cb 4c c8 12 \tsha256rnds2 %xmm0,0x12(%rax,%rcx,8),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x88, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cb 88 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rax),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8d, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cb 8d 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rbp),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c 01 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rcx,%rax,1),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c 05 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rbp,%rax,1),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c 08 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rax,%rcx,1),%xmm1",},
-{{0x0f, 0x38, 0xcb, 0x8c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cb 8c c8 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rax,%rcx,8),%xmm1",},
-{{0x44, 0x0f, 0x38, 0xcb, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
-"44 0f 38 cb bc c8 78 56 34 12 \tsha256rnds2 %xmm0,0x12345678(%rax,%rcx,8),%xmm15",},
-{{0x0f, 0x38, 0xcc, 0xc1, }, 4, 0, "", "",
-"0f 38 cc c1 \tsha256msg1 %xmm1,%xmm0",},
-{{0x0f, 0x38, 0xcc, 0xd7, }, 4, 0, "", "",
-"0f 38 cc d7 \tsha256msg1 %xmm7,%xmm2",},
-{{0x41, 0x0f, 0x38, 0xcc, 0xc0, }, 5, 0, "", "",
-"41 0f 38 cc c0 \tsha256msg1 %xmm8,%xmm0",},
-{{0x44, 0x0f, 0x38, 0xcc, 0xc7, }, 5, 0, "", "",
-"44 0f 38 cc c7 \tsha256msg1 %xmm7,%xmm8",},
-{{0x45, 0x0f, 0x38, 0xcc, 0xc7, }, 5, 0, "", "",
-"45 0f 38 cc c7 \tsha256msg1 %xmm15,%xmm8",},
-{{0x0f, 0x38, 0xcc, 0x00, }, 4, 0, "", "",
-"0f 38 cc 00 \tsha256msg1 (%rax),%xmm0",},
-{{0x41, 0x0f, 0x38, 0xcc, 0x00, }, 5, 0, "", "",
-"41 0f 38 cc 00 \tsha256msg1 (%r8),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 04 25 78 56 34 12 \tsha256msg1 0x12345678,%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x18, }, 4, 0, "", "",
-"0f 38 cc 18 \tsha256msg1 (%rax),%xmm3",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x01, }, 5, 0, "", "",
-"0f 38 cc 04 01 \tsha256msg1 (%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 04 05 78 56 34 12 \tsha256msg1 0x12345678(,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0x08, }, 5, 0, "", "",
-"0f 38 cc 04 08 \tsha256msg1 (%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x04, 0xc8, }, 5, 0, "", "",
-"0f 38 cc 04 c8 \tsha256msg1 (%rax,%rcx,8),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x40, 0x12, }, 5, 0, "", "",
-"0f 38 cc 40 12 \tsha256msg1 0x12(%rax),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x45, 0x12, }, 5, 0, "", "",
-"0f 38 cc 45 12 \tsha256msg1 0x12(%rbp),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 01 12 \tsha256msg1 0x12(%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 05 12 \tsha256msg1 0x12(%rbp,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 08 12 \tsha256msg1 0x12(%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"0f 38 cc 44 c8 12 \tsha256msg1 0x12(%rax,%rcx,8),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cc 80 78 56 34 12 \tsha256msg1 0x12345678(%rax),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cc 85 78 56 34 12 \tsha256msg1 0x12345678(%rbp),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 01 78 56 34 12 \tsha256msg1 0x12345678(%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 05 78 56 34 12 \tsha256msg1 0x12345678(%rbp,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 08 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcc, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cc 84 c8 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,8),%xmm0",},
-{{0x44, 0x0f, 0x38, 0xcc, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
-"44 0f 38 cc bc c8 78 56 34 12 \tsha256msg1 0x12345678(%rax,%rcx,8),%xmm15",},
-{{0x0f, 0x38, 0xcd, 0xc1, }, 4, 0, "", "",
-"0f 38 cd c1 \tsha256msg2 %xmm1,%xmm0",},
-{{0x0f, 0x38, 0xcd, 0xd7, }, 4, 0, "", "",
-"0f 38 cd d7 \tsha256msg2 %xmm7,%xmm2",},
-{{0x41, 0x0f, 0x38, 0xcd, 0xc0, }, 5, 0, "", "",
-"41 0f 38 cd c0 \tsha256msg2 %xmm8,%xmm0",},
-{{0x44, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
-"44 0f 38 cd c7 \tsha256msg2 %xmm7,%xmm8",},
-{{0x45, 0x0f, 0x38, 0xcd, 0xc7, }, 5, 0, "", "",
-"45 0f 38 cd c7 \tsha256msg2 %xmm15,%xmm8",},
-{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "",
-"0f 38 cd 00 \tsha256msg2 (%rax),%xmm0",},
-{{0x41, 0x0f, 0x38, 0xcd, 0x00, }, 5, 0, "", "",
-"41 0f 38 cd 00 \tsha256msg2 (%r8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 04 25 78 56 34 12 \tsha256msg2 0x12345678,%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "",
-"0f 38 cd 18 \tsha256msg2 (%rax),%xmm3",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "",
-"0f 38 cd 04 01 \tsha256msg2 (%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "",
-"0f 38 cd 04 08 \tsha256msg2 (%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "",
-"0f 38 cd 04 c8 \tsha256msg2 (%rax,%rcx,8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "",
-"0f 38 cd 40 12 \tsha256msg2 0x12(%rax),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "",
-"0f 38 cd 45 12 \tsha256msg2 0x12(%rbp),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 01 12 \tsha256msg2 0x12(%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 05 12 \tsha256msg2 0x12(%rbp,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 08 12 \tsha256msg2 0x12(%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "",
-"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%rax,%rcx,8),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%rax),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%rbp),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%rcx,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%rbp,%rax,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,1),%xmm0",},
-{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm0",},
-{{0x44, 0x0f, 0x38, 0xcd, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
-"44 0f 38 cd bc c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm15",},
-{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
-"66 0f ae 38 \tclflushopt (%rax)",},
-{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "",
-"66 41 0f ae 38 \tclflushopt (%r8)",},
-{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",},
-{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",},
-{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
-"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",},
-{{0x0f, 0xae, 0x38, }, 3, 0, "", "",
-"0f ae 38 \tclflush (%rax)",},
-{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "",
-"41 0f ae 38 \tclflush (%r8)",},
-{{0x0f, 0xae, 0xf8, }, 3, 0, "", "",
-"0f ae f8 \tsfence ",},
-{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
-"66 0f ae 30 \tclwb (%rax)",},
-{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "",
-"66 41 0f ae 30 \tclwb (%r8)",},
-{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",},
-{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",},
-{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "",
-"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",},
-{{0x0f, 0xae, 0x30, }, 3, 0, "", "",
-"0f ae 30 \txsaveopt (%rax)",},
-{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "",
-"41 0f ae 30 \txsaveopt (%r8)",},
-{{0x0f, 0xae, 0xf0, }, 3, 0, "", "",
-"0f ae f0 \tmfence ",},
-{{0x0f, 0xc7, 0x20, }, 3, 0, "", "",
-"0f c7 20 \txsavec (%rax)",},
-{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "",
-"41 0f c7 20 \txsavec (%r8)",},
-{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",},
-{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",},
-{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",},
-{{0x0f, 0xc7, 0x28, }, 3, 0, "", "",
-"0f c7 28 \txsaves (%rax)",},
-{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "",
-"41 0f c7 28 \txsaves (%r8)",},
-{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",},
-{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",},
-{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",},
-{{0x0f, 0xc7, 0x18, }, 3, 0, "", "",
-"0f c7 18 \txrstors (%rax)",},
-{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "",
-"41 0f c7 18 \txrstors (%r8)",},
-{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",},
-{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
-"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",},
-{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
-"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",},
-{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
-"66 0f ae f8 \tpcommit ",},
diff --git a/tools/perf/tests/insn-x86-dat-src.c b/tools/perf/tests/insn-x86-dat-src.c
deleted file mode 100644
index 41b1b1c62660..000000000000
--- a/tools/perf/tests/insn-x86-dat-src.c
+++ /dev/null
@@ -1,877 +0,0 @@
-/*
- * This file contains instructions for testing by the test titled:
- *
- * "Test x86 instruction decoder - new instructions"
- *
- * Note that the 'Expecting' comment lines are consumed by the
- * gen-insn-x86-dat.awk script and have the format:
- *
- * Expecting: <op> <branch> <rel>
- *
- * If this file is changed, remember to run the gen-insn-x86-dat.sh
- * script and commit the result.
- *
- * Refer to insn-x86.c for more details.
- */
-
-int main(void)
-{
- /* Following line is a marker for the awk script - do not change */
- asm volatile("rdtsc"); /* Start here */
-
-#ifdef __x86_64__
-
- /* bndmk m64, bnd */
-
- asm volatile("bndmk (%rax), %bnd0");
- asm volatile("bndmk (%r8), %bnd0");
- asm volatile("bndmk (0x12345678), %bnd0");
- asm volatile("bndmk (%rax), %bnd3");
- asm volatile("bndmk (%rcx,%rax,1), %bnd0");
- asm volatile("bndmk 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndmk (%rax,%rcx,1), %bnd0");
- asm volatile("bndmk (%rax,%rcx,8), %bnd0");
- asm volatile("bndmk 0x12(%rax), %bnd0");
- asm volatile("bndmk 0x12(%rbp), %bnd0");
- asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0");
- asm volatile("bndmk 0x12345678(%rax), %bnd0");
- asm volatile("bndmk 0x12345678(%rbp), %bnd0");
- asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0");
- asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0");
-
- /* bndcl r/m64, bnd */
-
- asm volatile("bndcl (%rax), %bnd0");
- asm volatile("bndcl (%r8), %bnd0");
- asm volatile("bndcl (0x12345678), %bnd0");
- asm volatile("bndcl (%rax), %bnd3");
- asm volatile("bndcl (%rcx,%rax,1), %bnd0");
- asm volatile("bndcl 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndcl (%rax,%rcx,1), %bnd0");
- asm volatile("bndcl (%rax,%rcx,8), %bnd0");
- asm volatile("bndcl 0x12(%rax), %bnd0");
- asm volatile("bndcl 0x12(%rbp), %bnd0");
- asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0");
- asm volatile("bndcl 0x12345678(%rax), %bnd0");
- asm volatile("bndcl 0x12345678(%rbp), %bnd0");
- asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0");
- asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0");
- asm volatile("bndcl %rax, %bnd0");
-
- /* bndcu r/m64, bnd */
-
- asm volatile("bndcu (%rax), %bnd0");
- asm volatile("bndcu (%r8), %bnd0");
- asm volatile("bndcu (0x12345678), %bnd0");
- asm volatile("bndcu (%rax), %bnd3");
- asm volatile("bndcu (%rcx,%rax,1), %bnd0");
- asm volatile("bndcu 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndcu (%rax,%rcx,1), %bnd0");
- asm volatile("bndcu (%rax,%rcx,8), %bnd0");
- asm volatile("bndcu 0x12(%rax), %bnd0");
- asm volatile("bndcu 0x12(%rbp), %bnd0");
- asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0");
- asm volatile("bndcu 0x12345678(%rax), %bnd0");
- asm volatile("bndcu 0x12345678(%rbp), %bnd0");
- asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0");
- asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0");
- asm volatile("bndcu %rax, %bnd0");
-
- /* bndcn r/m64, bnd */
-
- asm volatile("bndcn (%rax), %bnd0");
- asm volatile("bndcn (%r8), %bnd0");
- asm volatile("bndcn (0x12345678), %bnd0");
- asm volatile("bndcn (%rax), %bnd3");
- asm volatile("bndcn (%rcx,%rax,1), %bnd0");
- asm volatile("bndcn 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndcn (%rax,%rcx,1), %bnd0");
- asm volatile("bndcn (%rax,%rcx,8), %bnd0");
- asm volatile("bndcn 0x12(%rax), %bnd0");
- asm volatile("bndcn 0x12(%rbp), %bnd0");
- asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0");
- asm volatile("bndcn 0x12345678(%rax), %bnd0");
- asm volatile("bndcn 0x12345678(%rbp), %bnd0");
- asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0");
- asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0");
- asm volatile("bndcn %rax, %bnd0");
-
- /* bndmov m128, bnd */
-
- asm volatile("bndmov (%rax), %bnd0");
- asm volatile("bndmov (%r8), %bnd0");
- asm volatile("bndmov (0x12345678), %bnd0");
- asm volatile("bndmov (%rax), %bnd3");
- asm volatile("bndmov (%rcx,%rax,1), %bnd0");
- asm volatile("bndmov 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndmov (%rax,%rcx,1), %bnd0");
- asm volatile("bndmov (%rax,%rcx,8), %bnd0");
- asm volatile("bndmov 0x12(%rax), %bnd0");
- asm volatile("bndmov 0x12(%rbp), %bnd0");
- asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0");
- asm volatile("bndmov 0x12345678(%rax), %bnd0");
- asm volatile("bndmov 0x12345678(%rbp), %bnd0");
- asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0");
- asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0");
-
- /* bndmov bnd, m128 */
-
- asm volatile("bndmov %bnd0, (%rax)");
- asm volatile("bndmov %bnd0, (%r8)");
- asm volatile("bndmov %bnd0, (0x12345678)");
- asm volatile("bndmov %bnd3, (%rax)");
- asm volatile("bndmov %bnd0, (%rcx,%rax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)");
- asm volatile("bndmov %bnd0, (%rax,%rcx,1)");
- asm volatile("bndmov %bnd0, (%rax,%rcx,8)");
- asm volatile("bndmov %bnd0, 0x12(%rax)");
- asm volatile("bndmov %bnd0, 0x12(%rbp)");
- asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)");
- asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)");
- asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)");
- asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)");
- asm volatile("bndmov %bnd0, 0x12345678(%rax)");
- asm volatile("bndmov %bnd0, 0x12345678(%rbp)");
- asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)");
-
- /* bndmov bnd2, bnd1 */
-
- asm volatile("bndmov %bnd0, %bnd1");
- asm volatile("bndmov %bnd1, %bnd0");
-
- /* bndldx mib, bnd */
-
- asm volatile("bndldx (%rax), %bnd0");
- asm volatile("bndldx (%r8), %bnd0");
- asm volatile("bndldx (0x12345678), %bnd0");
- asm volatile("bndldx (%rax), %bnd3");
- asm volatile("bndldx (%rcx,%rax,1), %bnd0");
- asm volatile("bndldx 0x12345678(,%rax,1), %bnd0");
- asm volatile("bndldx (%rax,%rcx,1), %bnd0");
- asm volatile("bndldx 0x12(%rax), %bnd0");
- asm volatile("bndldx 0x12(%rbp), %bnd0");
- asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0");
- asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0");
- asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0");
- asm volatile("bndldx 0x12345678(%rax), %bnd0");
- asm volatile("bndldx 0x12345678(%rbp), %bnd0");
- asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0");
- asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0");
- asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0");
-
- /* bndstx bnd, mib */
-
- asm volatile("bndstx %bnd0, (%rax)");
- asm volatile("bndstx %bnd0, (%r8)");
- asm volatile("bndstx %bnd0, (0x12345678)");
- asm volatile("bndstx %bnd3, (%rax)");
- asm volatile("bndstx %bnd0, (%rcx,%rax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)");
- asm volatile("bndstx %bnd0, (%rax,%rcx,1)");
- asm volatile("bndstx %bnd0, 0x12(%rax)");
- asm volatile("bndstx %bnd0, 0x12(%rbp)");
- asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)");
- asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)");
- asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%rax)");
- asm volatile("bndstx %bnd0, 0x12345678(%rbp)");
- asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)");
-
- /* bnd prefix on call, ret, jmp and all jcc */
-
- asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */
- asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
- asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
- asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
- asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */
- asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
- asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */
-
- /* sha1rnds4 imm8, xmm2/m128, xmm1 */
-
- asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
- asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
- asm volatile("sha1rnds4 $0x91, %xmm8, %xmm0");
- asm volatile("sha1rnds4 $0x91, %xmm7, %xmm8");
- asm volatile("sha1rnds4 $0x91, %xmm15, %xmm8");
- asm volatile("sha1rnds4 $0x91, (%rax), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%r8), %xmm0");
- asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%rax), %xmm3");
- asm volatile("sha1rnds4 $0x91, (%rcx,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%rax,%rcx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%rax,%rcx,8), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rax), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rbp), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rax), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha1nexte xmm2/m128, xmm1 */
-
- asm volatile("sha1nexte %xmm1, %xmm0");
- asm volatile("sha1nexte %xmm7, %xmm2");
- asm volatile("sha1nexte %xmm8, %xmm0");
- asm volatile("sha1nexte %xmm7, %xmm8");
- asm volatile("sha1nexte %xmm15, %xmm8");
- asm volatile("sha1nexte (%rax), %xmm0");
- asm volatile("sha1nexte (%r8), %xmm0");
- asm volatile("sha1nexte (0x12345678), %xmm0");
- asm volatile("sha1nexte (%rax), %xmm3");
- asm volatile("sha1nexte (%rcx,%rax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha1nexte (%rax,%rcx,1), %xmm0");
- asm volatile("sha1nexte (%rax,%rcx,8), %xmm0");
- asm volatile("sha1nexte 0x12(%rax), %xmm0");
- asm volatile("sha1nexte 0x12(%rbp), %xmm0");
- asm volatile("sha1nexte 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha1nexte 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha1nexte 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha1nexte 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rax), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rbp), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha1msg1 xmm2/m128, xmm1 */
-
- asm volatile("sha1msg1 %xmm1, %xmm0");
- asm volatile("sha1msg1 %xmm7, %xmm2");
- asm volatile("sha1msg1 %xmm8, %xmm0");
- asm volatile("sha1msg1 %xmm7, %xmm8");
- asm volatile("sha1msg1 %xmm15, %xmm8");
- asm volatile("sha1msg1 (%rax), %xmm0");
- asm volatile("sha1msg1 (%r8), %xmm0");
- asm volatile("sha1msg1 (0x12345678), %xmm0");
- asm volatile("sha1msg1 (%rax), %xmm3");
- asm volatile("sha1msg1 (%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha1msg1 (%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg1 (%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg1 0x12(%rax), %xmm0");
- asm volatile("sha1msg1 0x12(%rbp), %xmm0");
- asm volatile("sha1msg1 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg1 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha1msg1 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg1 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rax), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rbp), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha1msg2 xmm2/m128, xmm1 */
-
- asm volatile("sha1msg2 %xmm1, %xmm0");
- asm volatile("sha1msg2 %xmm7, %xmm2");
- asm volatile("sha1msg2 %xmm8, %xmm0");
- asm volatile("sha1msg2 %xmm7, %xmm8");
- asm volatile("sha1msg2 %xmm15, %xmm8");
- asm volatile("sha1msg2 (%rax), %xmm0");
- asm volatile("sha1msg2 (%r8), %xmm0");
- asm volatile("sha1msg2 (0x12345678), %xmm0");
- asm volatile("sha1msg2 (%rax), %xmm3");
- asm volatile("sha1msg2 (%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha1msg2 (%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg2 (%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg2 0x12(%rax), %xmm0");
- asm volatile("sha1msg2 0x12(%rbp), %xmm0");
- asm volatile("sha1msg2 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg2 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha1msg2 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg2 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rax), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rbp), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
- /* Note sha256rnds2 has an implicit operand 'xmm0' */
-
- asm volatile("sha256rnds2 %xmm4, %xmm1");
- asm volatile("sha256rnds2 %xmm7, %xmm2");
- asm volatile("sha256rnds2 %xmm8, %xmm1");
- asm volatile("sha256rnds2 %xmm7, %xmm8");
- asm volatile("sha256rnds2 %xmm15, %xmm8");
- asm volatile("sha256rnds2 (%rax), %xmm1");
- asm volatile("sha256rnds2 (%r8), %xmm1");
- asm volatile("sha256rnds2 (0x12345678), %xmm1");
- asm volatile("sha256rnds2 (%rax), %xmm3");
- asm volatile("sha256rnds2 (%rcx,%rax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(,%rax,1), %xmm1");
- asm volatile("sha256rnds2 (%rax,%rcx,1), %xmm1");
- asm volatile("sha256rnds2 (%rax,%rcx,8), %xmm1");
- asm volatile("sha256rnds2 0x12(%rax), %xmm1");
- asm volatile("sha256rnds2 0x12(%rbp), %xmm1");
- asm volatile("sha256rnds2 0x12(%rcx,%rax,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%rbp,%rax,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%rax,%rcx,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%rax,%rcx,8), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rax), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rbp), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rcx,%rax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rbp,%rax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rax,%rcx,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha256msg1 xmm2/m128, xmm1 */
-
- asm volatile("sha256msg1 %xmm1, %xmm0");
- asm volatile("sha256msg1 %xmm7, %xmm2");
- asm volatile("sha256msg1 %xmm8, %xmm0");
- asm volatile("sha256msg1 %xmm7, %xmm8");
- asm volatile("sha256msg1 %xmm15, %xmm8");
- asm volatile("sha256msg1 (%rax), %xmm0");
- asm volatile("sha256msg1 (%r8), %xmm0");
- asm volatile("sha256msg1 (0x12345678), %xmm0");
- asm volatile("sha256msg1 (%rax), %xmm3");
- asm volatile("sha256msg1 (%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha256msg1 (%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg1 (%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg1 0x12(%rax), %xmm0");
- asm volatile("sha256msg1 0x12(%rbp), %xmm0");
- asm volatile("sha256msg1 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg1 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha256msg1 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg1 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rax), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rbp), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* sha256msg2 xmm2/m128, xmm1 */
-
- asm volatile("sha256msg2 %xmm1, %xmm0");
- asm volatile("sha256msg2 %xmm7, %xmm2");
- asm volatile("sha256msg2 %xmm8, %xmm0");
- asm volatile("sha256msg2 %xmm7, %xmm8");
- asm volatile("sha256msg2 %xmm15, %xmm8");
- asm volatile("sha256msg2 (%rax), %xmm0");
- asm volatile("sha256msg2 (%r8), %xmm0");
- asm volatile("sha256msg2 (0x12345678), %xmm0");
- asm volatile("sha256msg2 (%rax), %xmm3");
- asm volatile("sha256msg2 (%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(,%rax,1), %xmm0");
- asm volatile("sha256msg2 (%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg2 (%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg2 0x12(%rax), %xmm0");
- asm volatile("sha256msg2 0x12(%rbp), %xmm0");
- asm volatile("sha256msg2 0x12(%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg2 0x12(%rbp,%rax,1), %xmm0");
- asm volatile("sha256msg2 0x12(%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg2 0x12(%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rax), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rbp), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rcx,%rax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rbp,%rax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rax,%rcx,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0");
- asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15");
-
- /* clflushopt m8 */
-
- asm volatile("clflushopt (%rax)");
- asm volatile("clflushopt (%r8)");
- asm volatile("clflushopt (0x12345678)");
- asm volatile("clflushopt 0x12345678(%rax,%rcx,8)");
- asm volatile("clflushopt 0x12345678(%r8,%rcx,8)");
- /* Also check instructions in the same group encoding as clflushopt */
- asm volatile("clflush (%rax)");
- asm volatile("clflush (%r8)");
- asm volatile("sfence");
-
- /* clwb m8 */
-
- asm volatile("clwb (%rax)");
- asm volatile("clwb (%r8)");
- asm volatile("clwb (0x12345678)");
- asm volatile("clwb 0x12345678(%rax,%rcx,8)");
- asm volatile("clwb 0x12345678(%r8,%rcx,8)");
- /* Also check instructions in the same group encoding as clwb */
- asm volatile("xsaveopt (%rax)");
- asm volatile("xsaveopt (%r8)");
- asm volatile("mfence");
-
- /* xsavec mem */
-
- asm volatile("xsavec (%rax)");
- asm volatile("xsavec (%r8)");
- asm volatile("xsavec (0x12345678)");
- asm volatile("xsavec 0x12345678(%rax,%rcx,8)");
- asm volatile("xsavec 0x12345678(%r8,%rcx,8)");
-
- /* xsaves mem */
-
- asm volatile("xsaves (%rax)");
- asm volatile("xsaves (%r8)");
- asm volatile("xsaves (0x12345678)");
- asm volatile("xsaves 0x12345678(%rax,%rcx,8)");
- asm volatile("xsaves 0x12345678(%r8,%rcx,8)");
-
- /* xrstors mem */
-
- asm volatile("xrstors (%rax)");
- asm volatile("xrstors (%r8)");
- asm volatile("xrstors (0x12345678)");
- asm volatile("xrstors 0x12345678(%rax,%rcx,8)");
- asm volatile("xrstors 0x12345678(%r8,%rcx,8)");
-
-#else /* #ifdef __x86_64__ */
-
- /* bndmk m32, bnd */
-
- asm volatile("bndmk (%eax), %bnd0");
- asm volatile("bndmk (0x12345678), %bnd0");
- asm volatile("bndmk (%eax), %bnd3");
- asm volatile("bndmk (%ecx,%eax,1), %bnd0");
- asm volatile("bndmk 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndmk (%eax,%ecx,1), %bnd0");
- asm volatile("bndmk (%eax,%ecx,8), %bnd0");
- asm volatile("bndmk 0x12(%eax), %bnd0");
- asm volatile("bndmk 0x12(%ebp), %bnd0");
- asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0");
- asm volatile("bndmk 0x12345678(%eax), %bnd0");
- asm volatile("bndmk 0x12345678(%ebp), %bnd0");
- asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0");
- asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0");
-
- /* bndcl r/m32, bnd */
-
- asm volatile("bndcl (%eax), %bnd0");
- asm volatile("bndcl (0x12345678), %bnd0");
- asm volatile("bndcl (%eax), %bnd3");
- asm volatile("bndcl (%ecx,%eax,1), %bnd0");
- asm volatile("bndcl 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndcl (%eax,%ecx,1), %bnd0");
- asm volatile("bndcl (%eax,%ecx,8), %bnd0");
- asm volatile("bndcl 0x12(%eax), %bnd0");
- asm volatile("bndcl 0x12(%ebp), %bnd0");
- asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0");
- asm volatile("bndcl 0x12345678(%eax), %bnd0");
- asm volatile("bndcl 0x12345678(%ebp), %bnd0");
- asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0");
- asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0");
- asm volatile("bndcl %eax, %bnd0");
-
- /* bndcu r/m32, bnd */
-
- asm volatile("bndcu (%eax), %bnd0");
- asm volatile("bndcu (0x12345678), %bnd0");
- asm volatile("bndcu (%eax), %bnd3");
- asm volatile("bndcu (%ecx,%eax,1), %bnd0");
- asm volatile("bndcu 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndcu (%eax,%ecx,1), %bnd0");
- asm volatile("bndcu (%eax,%ecx,8), %bnd0");
- asm volatile("bndcu 0x12(%eax), %bnd0");
- asm volatile("bndcu 0x12(%ebp), %bnd0");
- asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0");
- asm volatile("bndcu 0x12345678(%eax), %bnd0");
- asm volatile("bndcu 0x12345678(%ebp), %bnd0");
- asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0");
- asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0");
- asm volatile("bndcu %eax, %bnd0");
-
- /* bndcn r/m32, bnd */
-
- asm volatile("bndcn (%eax), %bnd0");
- asm volatile("bndcn (0x12345678), %bnd0");
- asm volatile("bndcn (%eax), %bnd3");
- asm volatile("bndcn (%ecx,%eax,1), %bnd0");
- asm volatile("bndcn 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndcn (%eax,%ecx,1), %bnd0");
- asm volatile("bndcn (%eax,%ecx,8), %bnd0");
- asm volatile("bndcn 0x12(%eax), %bnd0");
- asm volatile("bndcn 0x12(%ebp), %bnd0");
- asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0");
- asm volatile("bndcn 0x12345678(%eax), %bnd0");
- asm volatile("bndcn 0x12345678(%ebp), %bnd0");
- asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0");
- asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0");
- asm volatile("bndcn %eax, %bnd0");
-
- /* bndmov m64, bnd */
-
- asm volatile("bndmov (%eax), %bnd0");
- asm volatile("bndmov (0x12345678), %bnd0");
- asm volatile("bndmov (%eax), %bnd3");
- asm volatile("bndmov (%ecx,%eax,1), %bnd0");
- asm volatile("bndmov 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndmov (%eax,%ecx,1), %bnd0");
- asm volatile("bndmov (%eax,%ecx,8), %bnd0");
- asm volatile("bndmov 0x12(%eax), %bnd0");
- asm volatile("bndmov 0x12(%ebp), %bnd0");
- asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0");
- asm volatile("bndmov 0x12345678(%eax), %bnd0");
- asm volatile("bndmov 0x12345678(%ebp), %bnd0");
- asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0");
- asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0");
-
- /* bndmov bnd, m64 */
-
- asm volatile("bndmov %bnd0, (%eax)");
- asm volatile("bndmov %bnd0, (0x12345678)");
- asm volatile("bndmov %bnd3, (%eax)");
- asm volatile("bndmov %bnd0, (%ecx,%eax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)");
- asm volatile("bndmov %bnd0, (%eax,%ecx,1)");
- asm volatile("bndmov %bnd0, (%eax,%ecx,8)");
- asm volatile("bndmov %bnd0, 0x12(%eax)");
- asm volatile("bndmov %bnd0, 0x12(%ebp)");
- asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)");
- asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)");
- asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)");
- asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)");
- asm volatile("bndmov %bnd0, 0x12345678(%eax)");
- asm volatile("bndmov %bnd0, 0x12345678(%ebp)");
- asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)");
- asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)");
-
- /* bndmov bnd2, bnd1 */
-
- asm volatile("bndmov %bnd0, %bnd1");
- asm volatile("bndmov %bnd1, %bnd0");
-
- /* bndldx mib, bnd */
-
- asm volatile("bndldx (%eax), %bnd0");
- asm volatile("bndldx (0x12345678), %bnd0");
- asm volatile("bndldx (%eax), %bnd3");
- asm volatile("bndldx (%ecx,%eax,1), %bnd0");
- asm volatile("bndldx 0x12345678(,%eax,1), %bnd0");
- asm volatile("bndldx (%eax,%ecx,1), %bnd0");
- asm volatile("bndldx 0x12(%eax), %bnd0");
- asm volatile("bndldx 0x12(%ebp), %bnd0");
- asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0");
- asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0");
- asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0");
- asm volatile("bndldx 0x12345678(%eax), %bnd0");
- asm volatile("bndldx 0x12345678(%ebp), %bnd0");
- asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0");
- asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0");
- asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0");
-
- /* bndstx bnd, mib */
-
- asm volatile("bndstx %bnd0, (%eax)");
- asm volatile("bndstx %bnd0, (0x12345678)");
- asm volatile("bndstx %bnd3, (%eax)");
- asm volatile("bndstx %bnd0, (%ecx,%eax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)");
- asm volatile("bndstx %bnd0, (%eax,%ecx,1)");
- asm volatile("bndstx %bnd0, 0x12(%eax)");
- asm volatile("bndstx %bnd0, 0x12(%ebp)");
- asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)");
- asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)");
- asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%eax)");
- asm volatile("bndstx %bnd0, 0x12345678(%ebp)");
- asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)");
- asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)");
-
- /* bnd prefix on call, ret, jmp and all jcc */
-
- asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */
- asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */
- asm volatile("bnd ret"); /* Expecting: ret indirect 0 */
- asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
- asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */
- asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */
- asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */
-
- /* sha1rnds4 imm8, xmm2/m128, xmm1 */
-
- asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0");
- asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2");
- asm volatile("sha1rnds4 $0x91, (%eax), %xmm0");
- asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%eax), %xmm3");
- asm volatile("sha1rnds4 $0x91, (%ecx,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%eax,%ecx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, (%eax,%ecx,8), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%eax), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%ebp), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%eax), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* sha1nexte xmm2/m128, xmm1 */
-
- asm volatile("sha1nexte %xmm1, %xmm0");
- asm volatile("sha1nexte %xmm7, %xmm2");
- asm volatile("sha1nexte (%eax), %xmm0");
- asm volatile("sha1nexte (0x12345678), %xmm0");
- asm volatile("sha1nexte (%eax), %xmm3");
- asm volatile("sha1nexte (%ecx,%eax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha1nexte (%eax,%ecx,1), %xmm0");
- asm volatile("sha1nexte (%eax,%ecx,8), %xmm0");
- asm volatile("sha1nexte 0x12(%eax), %xmm0");
- asm volatile("sha1nexte 0x12(%ebp), %xmm0");
- asm volatile("sha1nexte 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha1nexte 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha1nexte 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha1nexte 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha1nexte 0x12345678(%eax), %xmm0");
- asm volatile("sha1nexte 0x12345678(%ebp), %xmm0");
- asm volatile("sha1nexte 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha1nexte 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* sha1msg1 xmm2/m128, xmm1 */
-
- asm volatile("sha1msg1 %xmm1, %xmm0");
- asm volatile("sha1msg1 %xmm7, %xmm2");
- asm volatile("sha1msg1 (%eax), %xmm0");
- asm volatile("sha1msg1 (0x12345678), %xmm0");
- asm volatile("sha1msg1 (%eax), %xmm3");
- asm volatile("sha1msg1 (%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha1msg1 (%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg1 (%eax,%ecx,8), %xmm0");
- asm volatile("sha1msg1 0x12(%eax), %xmm0");
- asm volatile("sha1msg1 0x12(%ebp), %xmm0");
- asm volatile("sha1msg1 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg1 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha1msg1 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg1 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha1msg1 0x12345678(%eax), %xmm0");
- asm volatile("sha1msg1 0x12345678(%ebp), %xmm0");
- asm volatile("sha1msg1 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg1 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* sha1msg2 xmm2/m128, xmm1 */
-
- asm volatile("sha1msg2 %xmm1, %xmm0");
- asm volatile("sha1msg2 %xmm7, %xmm2");
- asm volatile("sha1msg2 (%eax), %xmm0");
- asm volatile("sha1msg2 (0x12345678), %xmm0");
- asm volatile("sha1msg2 (%eax), %xmm3");
- asm volatile("sha1msg2 (%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha1msg2 (%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg2 (%eax,%ecx,8), %xmm0");
- asm volatile("sha1msg2 0x12(%eax), %xmm0");
- asm volatile("sha1msg2 0x12(%ebp), %xmm0");
- asm volatile("sha1msg2 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg2 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha1msg2 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg2 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha1msg2 0x12345678(%eax), %xmm0");
- asm volatile("sha1msg2 0x12345678(%ebp), %xmm0");
- asm volatile("sha1msg2 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha1msg2 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* sha256rnds2 <XMM0>, xmm2/m128, xmm1 */
- /* Note sha256rnds2 has an implicit operand 'xmm0' */
-
- asm volatile("sha256rnds2 %xmm4, %xmm1");
- asm volatile("sha256rnds2 %xmm7, %xmm2");
- asm volatile("sha256rnds2 (%eax), %xmm1");
- asm volatile("sha256rnds2 (0x12345678), %xmm1");
- asm volatile("sha256rnds2 (%eax), %xmm3");
- asm volatile("sha256rnds2 (%ecx,%eax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(,%eax,1), %xmm1");
- asm volatile("sha256rnds2 (%eax,%ecx,1), %xmm1");
- asm volatile("sha256rnds2 (%eax,%ecx,8), %xmm1");
- asm volatile("sha256rnds2 0x12(%eax), %xmm1");
- asm volatile("sha256rnds2 0x12(%ebp), %xmm1");
- asm volatile("sha256rnds2 0x12(%ecx,%eax,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%ebp,%eax,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%eax,%ecx,1), %xmm1");
- asm volatile("sha256rnds2 0x12(%eax,%ecx,8), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%eax), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%ebp), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%ecx,%eax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%ebp,%eax,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%eax,%ecx,1), %xmm1");
- asm volatile("sha256rnds2 0x12345678(%eax,%ecx,8), %xmm1");
-
- /* sha256msg1 xmm2/m128, xmm1 */
-
- asm volatile("sha256msg1 %xmm1, %xmm0");
- asm volatile("sha256msg1 %xmm7, %xmm2");
- asm volatile("sha256msg1 (%eax), %xmm0");
- asm volatile("sha256msg1 (0x12345678), %xmm0");
- asm volatile("sha256msg1 (%eax), %xmm3");
- asm volatile("sha256msg1 (%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha256msg1 (%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg1 (%eax,%ecx,8), %xmm0");
- asm volatile("sha256msg1 0x12(%eax), %xmm0");
- asm volatile("sha256msg1 0x12(%ebp), %xmm0");
- asm volatile("sha256msg1 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg1 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha256msg1 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg1 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha256msg1 0x12345678(%eax), %xmm0");
- asm volatile("sha256msg1 0x12345678(%ebp), %xmm0");
- asm volatile("sha256msg1 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg1 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* sha256msg2 xmm2/m128, xmm1 */
-
- asm volatile("sha256msg2 %xmm1, %xmm0");
- asm volatile("sha256msg2 %xmm7, %xmm2");
- asm volatile("sha256msg2 (%eax), %xmm0");
- asm volatile("sha256msg2 (0x12345678), %xmm0");
- asm volatile("sha256msg2 (%eax), %xmm3");
- asm volatile("sha256msg2 (%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(,%eax,1), %xmm0");
- asm volatile("sha256msg2 (%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg2 (%eax,%ecx,8), %xmm0");
- asm volatile("sha256msg2 0x12(%eax), %xmm0");
- asm volatile("sha256msg2 0x12(%ebp), %xmm0");
- asm volatile("sha256msg2 0x12(%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg2 0x12(%ebp,%eax,1), %xmm0");
- asm volatile("sha256msg2 0x12(%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg2 0x12(%eax,%ecx,8), %xmm0");
- asm volatile("sha256msg2 0x12345678(%eax), %xmm0");
- asm volatile("sha256msg2 0x12345678(%ebp), %xmm0");
- asm volatile("sha256msg2 0x12345678(%ecx,%eax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%ebp,%eax,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0");
- asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0");
-
- /* clflushopt m8 */
-
- asm volatile("clflushopt (%eax)");
- asm volatile("clflushopt (0x12345678)");
- asm volatile("clflushopt 0x12345678(%eax,%ecx,8)");
- /* Also check instructions in the same group encoding as clflushopt */
- asm volatile("clflush (%eax)");
- asm volatile("sfence");
-
- /* clwb m8 */
-
- asm volatile("clwb (%eax)");
- asm volatile("clwb (0x12345678)");
- asm volatile("clwb 0x12345678(%eax,%ecx,8)");
- /* Also check instructions in the same group encoding as clwb */
- asm volatile("xsaveopt (%eax)");
- asm volatile("mfence");
-
- /* xsavec mem */
-
- asm volatile("xsavec (%eax)");
- asm volatile("xsavec (0x12345678)");
- asm volatile("xsavec 0x12345678(%eax,%ecx,8)");
-
- /* xsaves mem */
-
- asm volatile("xsaves (%eax)");
- asm volatile("xsaves (0x12345678)");
- asm volatile("xsaves 0x12345678(%eax,%ecx,8)");
-
- /* xrstors mem */
-
- asm volatile("xrstors (%eax)");
- asm volatile("xrstors (0x12345678)");
- asm volatile("xrstors 0x12345678(%eax,%ecx,8)");
-
-#endif /* #ifndef __x86_64__ */
-
- /* pcommit */
-
- asm volatile("pcommit");
-
- /* Following line is a marker for the awk script - do not change */
- asm volatile("rdtsc"); /* Stop here */
-
- return 0;
-}
diff --git a/tools/perf/tests/insn-x86.c b/tools/perf/tests/insn-x86.c
deleted file mode 100644
index 5c49eec81349..000000000000
--- a/tools/perf/tests/insn-x86.c
+++ /dev/null
@@ -1,184 +0,0 @@
-#include <linux/types.h>
-
-#include "debug.h"
-#include "tests.h"
-
-#include "intel-pt-decoder/insn.h"
-#include "intel-pt-decoder/intel-pt-insn-decoder.h"
-
-struct test_data {
- u8 data[MAX_INSN_SIZE];
- int expected_length;
- int expected_rel;
- const char *expected_op_str;
- const char *expected_branch_str;
- const char *asm_rep;
-};
-
-struct test_data test_data_32[] = {
-#include "insn-x86-dat-32.c"
- {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
- {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
- {{0}, 0, 0, NULL, NULL, NULL},
-};
-
-struct test_data test_data_64[] = {
-#include "insn-x86-dat-64.c"
- {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"},
- {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"},
- {{0}, 0, 0, NULL, NULL, NULL},
-};
-
-static int get_op(const char *op_str)
-{
- struct val_data {
- const char *name;
- int val;
- } vals[] = {
- {"other", INTEL_PT_OP_OTHER},
- {"call", INTEL_PT_OP_CALL},
- {"ret", INTEL_PT_OP_RET},
- {"jcc", INTEL_PT_OP_JCC},
- {"jmp", INTEL_PT_OP_JMP},
- {"loop", INTEL_PT_OP_LOOP},
- {"iret", INTEL_PT_OP_IRET},
- {"int", INTEL_PT_OP_INT},
- {"syscall", INTEL_PT_OP_SYSCALL},
- {"sysret", INTEL_PT_OP_SYSRET},
- {NULL, 0},
- };
- struct val_data *val;
-
- if (!op_str || !strlen(op_str))
- return 0;
-
- for (val = vals; val->name; val++) {
- if (!strcmp(val->name, op_str))
- return val->val;
- }
-
- pr_debug("Failed to get op\n");
-
- return -1;
-}
-
-static int get_branch(const char *branch_str)
-{
- struct val_data {
- const char *name;
- int val;
- } vals[] = {
- {"no_branch", INTEL_PT_BR_NO_BRANCH},
- {"indirect", INTEL_PT_BR_INDIRECT},
- {"conditional", INTEL_PT_BR_CONDITIONAL},
- {"unconditional", INTEL_PT_BR_UNCONDITIONAL},
- {NULL, 0},
- };
- struct val_data *val;
-
- if (!branch_str || !strlen(branch_str))
- return 0;
-
- for (val = vals; val->name; val++) {
- if (!strcmp(val->name, branch_str))
- return val->val;
- }
-
- pr_debug("Failed to get branch\n");
-
- return -1;
-}
-
-static int test_data_item(struct test_data *dat, int x86_64)
-{
- struct intel_pt_insn intel_pt_insn;
- struct insn insn;
- int op, branch;
-
- insn_init(&insn, dat->data, MAX_INSN_SIZE, x86_64);
- insn_get_length(&insn);
-
- if (!insn_complete(&insn)) {
- pr_debug("Failed to decode: %s\n", dat->asm_rep);
- return -1;
- }
-
- if (insn.length != dat->expected_length) {
- pr_debug("Failed to decode length (%d vs expected %d): %s\n",
- insn.length, dat->expected_length, dat->asm_rep);
- return -1;
- }
-
- op = get_op(dat->expected_op_str);
- branch = get_branch(dat->expected_branch_str);
-
- if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) {
- pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep);
- return -1;
- }
-
- if ((int)intel_pt_insn.op != op) {
- pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n",
- intel_pt_insn.op, op, dat->asm_rep);
- return -1;
- }
-
- if ((int)intel_pt_insn.branch != branch) {
- pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n",
- intel_pt_insn.branch, branch, dat->asm_rep);
- return -1;
- }
-
- if (intel_pt_insn.rel != dat->expected_rel) {
- pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n",
- intel_pt_insn.rel, dat->expected_rel, dat->asm_rep);
- return -1;
- }
-
- pr_debug("Decoded ok: %s\n", dat->asm_rep);
-
- return 0;
-}
-
-static int test_data_set(struct test_data *dat_set, int x86_64)
-{
- struct test_data *dat;
- int ret = 0;
-
- for (dat = dat_set; dat->expected_length; dat++) {
- if (test_data_item(dat, x86_64))
- ret = -1;
- }
-
- return ret;
-}
-
-/**
- * test__insn_x86 - test x86 instruction decoder - new instructions.
- *
- * This function implements a test that decodes a selection of instructions and
- * checks the results. The Intel PT function that further categorizes
- * instructions (i.e. intel_pt_get_insn()) is also checked.
- *
- * The instructions are originally in insn-x86-dat-src.c which has been
- * processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce
- * insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program.
- * i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the
- * gen-insn-x86-dat.sh script, make perf, and then run the test.
- *
- * If the test passes %0 is returned, otherwise %-1 is returned. Use the
- * verbose (-v) option to see all the instructions and whether or not they
- * decoded successfuly.
- */
-int test__insn_x86(void)
-{
- int ret = 0;
-
- if (test_data_set(test_data_32, 0))
- ret = -1;
-
- if (test_data_set(test_data_64, 1))
- ret = -1;
-
- return ret;
-}
diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c
deleted file mode 100644
index 5f49484f1abc..000000000000
--- a/tools/perf/tests/perf-time-to-tsc.c
+++ /dev/null
@@ -1,162 +0,0 @@
-#include <stdio.h>
-#include <unistd.h>
-#include <linux/types.h>
-#include <sys/prctl.h>
-
-#include "parse-events.h"
-#include "evlist.h"
-#include "evsel.h"
-#include "thread_map.h"
-#include "cpumap.h"
-#include "tsc.h"
-#include "tests.h"
-
-#define CHECK__(x) { \
- while ((x) < 0) { \
- pr_debug(#x " failed!\n"); \
- goto out_err; \
- } \
-}
-
-#define CHECK_NOT_NULL__(x) { \
- while ((x) == NULL) { \
- pr_debug(#x " failed!\n"); \
- goto out_err; \
- } \
-}
-
-/**
- * test__perf_time_to_tsc - test converting perf time to TSC.
- *
- * This function implements a test that checks that the conversion of perf time
- * to and from TSC is consistent with the order of events. If the test passes
- * %0 is returned, otherwise %-1 is returned. If TSC conversion is not
- * supported then then the test passes but " (not supported)" is printed.
- */
-int test__perf_time_to_tsc(void)
-{
- struct record_opts opts = {
- .mmap_pages = UINT_MAX,
- .user_freq = UINT_MAX,
- .user_interval = ULLONG_MAX,
- .freq = 4000,
- .target = {
- .uses_mmap = true,
- },
- .sample_time = true,
- };
- struct thread_map *threads = NULL;
- struct cpu_map *cpus = NULL;
- struct perf_evlist *evlist = NULL;
- struct perf_evsel *evsel = NULL;
- int err = -1, ret, i;
- const char *comm1, *comm2;
- struct perf_tsc_conversion tc;
- struct perf_event_mmap_page *pc;
- union perf_event *event;
- u64 test_tsc, comm1_tsc, comm2_tsc;
- u64 test_time, comm1_time = 0, comm2_time = 0;
-
- threads = thread_map__new(-1, getpid(), UINT_MAX);
- CHECK_NOT_NULL__(threads);
-
- cpus = cpu_map__new(NULL);
- CHECK_NOT_NULL__(cpus);
-
- evlist = perf_evlist__new();
- CHECK_NOT_NULL__(evlist);
-
- perf_evlist__set_maps(evlist, cpus, threads);
-
- CHECK__(parse_events(evlist, "cycles:u", NULL));
-
- perf_evlist__config(evlist, &opts);
-
- evsel = perf_evlist__first(evlist);
-
- evsel->attr.comm = 1;
- evsel->attr.disabled = 1;
- evsel->attr.enable_on_exec = 0;
-
- CHECK__(perf_evlist__open(evlist));
-
- CHECK__(perf_evlist__mmap(evlist, UINT_MAX, false));
-
- pc = evlist->mmap[0].base;
- ret = perf_read_tsc_conversion(pc, &tc);
- if (ret) {
- if (ret == -EOPNOTSUPP) {
- fprintf(stderr, " (not supported)");
- return 0;
- }
- goto out_err;
- }
-
- perf_evlist__enable(evlist);
-
- comm1 = "Test COMM 1";
- CHECK__(prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0));
-
- test_tsc = rdtsc();
-
- comm2 = "Test COMM 2";
- CHECK__(prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0));
-
- perf_evlist__disable(evlist);
-
- for (i = 0; i < evlist->nr_mmaps; i++) {
- while ((event = perf_evlist__mmap_read(evlist, i)) != NULL) {
- struct perf_sample sample;
-
- if (event->header.type != PERF_RECORD_COMM ||
- (pid_t)event->comm.pid != getpid() ||
- (pid_t)event->comm.tid != getpid())
- goto next_event;
-
- if (strcmp(event->comm.comm, comm1) == 0) {
- CHECK__(perf_evsel__parse_sample(evsel, event,
- &sample));
- comm1_time = sample.time;
- }
- if (strcmp(event->comm.comm, comm2) == 0) {
- CHECK__(perf_evsel__parse_sample(evsel, event,
- &sample));
- comm2_time = sample.time;
- }
-next_event:
- perf_evlist__mmap_consume(evlist, i);
- }
- }
-
- if (!comm1_time || !comm2_time)
- goto out_err;
-
- test_time = tsc_to_perf_time(test_tsc, &tc);
- comm1_tsc = perf_time_to_tsc(comm1_time, &tc);
- comm2_tsc = perf_time_to_tsc(comm2_time, &tc);
-
- pr_debug("1st event perf time %"PRIu64" tsc %"PRIu64"\n",
- comm1_time, comm1_tsc);
- pr_debug("rdtsc time %"PRIu64" tsc %"PRIu64"\n",
- test_time, test_tsc);
- pr_debug("2nd event perf time %"PRIu64" tsc %"PRIu64"\n",
- comm2_time, comm2_tsc);
-
- if (test_time <= comm1_time ||
- test_time >= comm2_time)
- goto out_err;
-
- if (test_tsc <= comm1_tsc ||
- test_tsc >= comm2_tsc)
- goto out_err;
-
- err = 0;
-
-out_err:
- if (evlist) {
- perf_evlist__disable(evlist);
- perf_evlist__delete(evlist);
- }
-
- return err;
-}
diff --git a/tools/perf/tests/rdpmc.c b/tools/perf/tests/rdpmc.c
deleted file mode 100644
index d31f2c4d9f64..000000000000
--- a/tools/perf/tests/rdpmc.c
+++ /dev/null
@@ -1,177 +0,0 @@
-#include <unistd.h>
-#include <stdlib.h>
-#include <signal.h>
-#include <sys/mman.h>
-#include <linux/types.h>
-#include "perf.h"
-#include "debug.h"
-#include "tests.h"
-#include "cloexec.h"
-
-#if defined(__x86_64__) || defined(__i386__)
-
-static u64 rdpmc(unsigned int counter)
-{
- unsigned int low, high;
-
- asm volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (counter));
-
- return low | ((u64)high) << 32;
-}
-
-static u64 rdtsc(void)
-{
- unsigned int low, high;
-
- asm volatile("rdtsc" : "=a" (low), "=d" (high));
-
- return low | ((u64)high) << 32;
-}
-
-static u64 mmap_read_self(void *addr)
-{
- struct perf_event_mmap_page *pc = addr;
- u32 seq, idx, time_mult = 0, time_shift = 0;
- u64 count, cyc = 0, time_offset = 0, enabled, running, delta;
-
- do {
- seq = pc->lock;
- barrier();
-
- enabled = pc->time_enabled;
- running = pc->time_running;
-
- if (enabled != running) {
- cyc = rdtsc();
- time_mult = pc->time_mult;
- time_shift = pc->time_shift;
- time_offset = pc->time_offset;
- }
-
- idx = pc->index;
- count = pc->offset;
- if (idx)
- count += rdpmc(idx - 1);
-
- barrier();
- } while (pc->lock != seq);
-
- if (enabled != running) {
- u64 quot, rem;
-
- quot = (cyc >> time_shift);
- rem = cyc & ((1 << time_shift) - 1);
- delta = time_offset + quot * time_mult +
- ((rem * time_mult) >> time_shift);
-
- enabled += delta;
- if (idx)
- running += delta;
-
- quot = count / running;
- rem = count % running;
- count = quot * enabled + (rem * enabled) / running;
- }
-
- return count;
-}
-
-/*
- * If the RDPMC instruction faults then signal this back to the test parent task:
- */
-static void segfault_handler(int sig __maybe_unused,
- siginfo_t *info __maybe_unused,
- void *uc __maybe_unused)
-{
- exit(-1);
-}
-
-static int __test__rdpmc(void)
-{
- volatile int tmp = 0;
- u64 i, loops = 1000;
- int n;
- int fd;
- void *addr;
- struct perf_event_attr attr = {
- .type = PERF_TYPE_HARDWARE,
- .config = PERF_COUNT_HW_INSTRUCTIONS,
- .exclude_kernel = 1,
- };
- u64 delta_sum = 0;
- struct sigaction sa;
- char sbuf[STRERR_BUFSIZE];
-
- sigfillset(&sa.sa_mask);
- sa.sa_sigaction = segfault_handler;
- sigaction(SIGSEGV, &sa, NULL);
-
- fd = sys_perf_event_open(&attr, 0, -1, -1,
- perf_event_open_cloexec_flag());
- if (fd < 0) {
- pr_err("Error: sys_perf_event_open() syscall returned "
- "with %d (%s)\n", fd,
- strerror_r(errno, sbuf, sizeof(sbuf)));
- return -1;
- }
-
- addr = mmap(NULL, page_size, PROT_READ, MAP_SHARED, fd, 0);
- if (addr == (void *)(-1)) {
- pr_err("Error: mmap() syscall returned with (%s)\n",
- strerror_r(errno, sbuf, sizeof(sbuf)));
- goto out_close;
- }
-
- for (n = 0; n < 6; n++) {
- u64 stamp, now, delta;
-
- stamp = mmap_read_self(addr);
-
- for (i = 0; i < loops; i++)
- tmp++;
-
- now = mmap_read_self(addr);
- loops *= 10;
-
- delta = now - stamp;
- pr_debug("%14d: %14Lu\n", n, (long long)delta);
-
- delta_sum += delta;
- }
-
- munmap(addr, page_size);
- pr_debug(" ");
-out_close:
- close(fd);
-
- if (!delta_sum)
- return -1;
-
- return 0;
-}
-
-int test__rdpmc(void)
-{
- int status = 0;
- int wret = 0;
- int ret;
- int pid;
-
- pid = fork();
- if (pid < 0)
- return -1;
-
- if (!pid) {
- ret = __test__rdpmc();
-
- exit(ret);
- }
-
- wret = waitpid(pid, &status, 0);
- if (wret < 0 || status)
- return -1;
-
- return 0;
-}
-
-#endif
diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h
index b1cb1c081e3c..c80486969f83 100644
--- a/tools/perf/tests/tests.h
+++ b/tools/perf/tests/tests.h
@@ -35,7 +35,6 @@ int test__openat_syscall_event(void);
int test__openat_syscall_event_on_all_cpus(void);
int test__basic_mmap(void);
int test__PERF_RECORD(void);
-int test__rdpmc(void);
int test__perf_evsel__roundtrip_name_test(void);
int test__perf_evsel__tp_sched_test(void);
int test__syscall_openat_tp_fields(void);
@@ -51,7 +50,6 @@ int test__bp_signal(void);
int test__bp_signal_overflow(void);
int test__task_exit(void);
int test__sw_clock_freq(void);
-int test__perf_time_to_tsc(void);
int test__code_reading(void);
int test__sample_parsing(void);
int test__keep_tracking(void);
@@ -68,10 +66,9 @@ int test__fdarray__add(void);
int test__kmod_path__parse(void);
int test__thread_map(void);
int test__llvm(void);
-int test__insn_x86(void);
int test_session_topology(void);

-#if defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__)
#ifdef HAVE_DWARF_UNWIND_SUPPORT
struct thread;
struct perf_sample;
--
2.1.0

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