[PATCH 1/2] restore DPLL write

[Ville SyrjÃlÃ]

---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 147e700..f4fdff9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1743,6 +1743,8 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
 			   I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
 	}
 
+	I915_WRITE(reg, dpll);
+
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(reg);
 	udelay(150);
-- 
2.4.9


--R3G7APHDIzY6R/pk
Content-Type: text/x-diff; charset=us-ascii
Content-Disposition: attachment; filename="0002-enable-VGA-mode-before-P1-P2-write.patch"