[PATCH v2 2/2] clocksource: mmio: add devicetree support

[Mans Rullgard]

This implements the "clocksource-mmio" devicetree binding.  It is
useful for devices that have a free-running counter requiring no
setup.

Signed-off-by: Mans Rullgard <mans@xxxxxxxxx>
---
Changed in v2:
- added sched_clock support
---
 drivers/clocksource/mmio.c | 123 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 123 insertions(+)

diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
index 1593ade..b2cb3cc 100644
--- a/drivers/clocksource/mmio.c
+++ b/drivers/clocksource/mmio.c
@@ -5,9 +5,12 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/clk.h>
 #include <linux/clocksource.h>
 #include <linux/errno.h>
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/sched_clock.h>
 #include <linux/slab.h>
 
 struct clocksource_mmio {
@@ -71,3 +74,123 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
 
 	return clocksource_register_hz(&cs->clksrc, hz);
 }
+
+#ifdef CONFIG_OF
+static void __iomem *sched_clock_mmio_reg;
+
+static u64 notrace sched_clock_mmio_readl_up(void)
+{
+	return (u64)readl_relaxed(sched_clock_mmio_reg);
+}
+
+static u64 notrace sched_clock_mmio_readl_down(void)
+{
+	return ~(u64)readl_relaxed(sched_clock_mmio_reg);
+}
+
+static u64 notrace sched_clock_mmio_readw_up(void)
+{
+	return (u64)readw_relaxed(sched_clock_mmio_reg);
+}
+
+static u64 notrace sched_clock_mmio_readw_down(void)
+{
+	return ~(u64)readw_relaxed(sched_clock_mmio_reg);
+}
+
+static void __init clocksource_mmio_of_setup(struct device_node *node)
+{
+	cycle_t (*csrc_read)(struct clocksource *);
+	u64 (*sched_read)(void);
+	void __iomem *reg;
+	struct clk *clk;
+	const char *name;
+	unsigned long rate;
+	bool count_down;
+	u32 rating;
+	u32 width;
+	u32 bits;
+	int err;
+
+	if (of_property_read_u32(node, "reg-io-width", &width)) {
+		pr_err("clocksource-mmio: register width not specified\n");
+		return;
+	}
+
+	if (of_property_read_u32(node, "clocksource-bits", &bits)) {
+		pr_err("clocksource-mmio: bits not specified\n");
+		return;
+	}
+
+	if (of_property_read_u32(node, "clocksource-rating", &rating)) {
+		pr_err("clocksource-mmio: rating not specified\n");
+		return;
+	}
+
+	count_down = of_property_read_bool(node, "clocksource-counts-down");
+
+	if (width == 2) {
+		if (count_down) {
+			csrc_read = clocksource_mmio_readw_down;
+			sched_read = sched_clock_mmio_readw_down;
+		} else {
+			csrc_read = clocksource_mmio_readw_up;
+			sched_read = sched_clock_mmio_readw_up;
+		}
+	} else if (width == 4) {
+		if (count_down) {
+			csrc_read = clocksource_mmio_readl_down;
+			sched_read = sched_clock_mmio_readl_down;
+		} else {
+			csrc_read = clocksource_mmio_readl_up;
+			sched_read = sched_clock_mmio_readl_up;
+		}
+	} else {
+		pr_err("clocksource-mmio: reg-io-width must be 2 or 4\n");
+		return;
+	}
+
+	clk = of_clk_get(node, 0);
+	if (IS_ERR(clk)) {
+		pr_err("clocksource-mmio: failed to get clock\n");
+		return;
+	}
+
+	if (clk_prepare_enable(clk)) {
+		pr_err("clocksource-mmio: failed to enable clock\n");
+		return;
+	}
+
+	rate = clk_get_rate(clk);
+	if (!rate) {
+		pr_err("clocksource-mmio: clock rate is zero\n");
+		clk_disable_unprepare(clk);
+		return;
+	}
+
+	reg = of_iomap(node, 0);
+	if (!reg) {
+		pr_err("clocksource-mmio: iomap failed\n");
+		clk_disable_unprepare(clk);
+		return;
+	}
+
+	if (of_property_read_string(node, "label", &name))
+		name = node->name;
+
+	err = clocksource_mmio_init(reg, name, rate, rating, bits, csrc_read);
+	if (err) {
+		pr_err("clocksource-mmio: failed to register clock source\n");
+		clk_disable_unprepare(clk);
+		iounmap(reg);
+		return;
+	}
+
+	if (of_property_read_bool(node, "linux,sched-clock")) {
+		sched_clock_mmio_reg = reg;
+		sched_clock_register(sched_read, bits, rate);
+	}
+}
+CLOCKSOURCE_OF_DECLARE(clocksource_mmio, "clocksource-mmio",
+		       clocksource_mmio_of_setup);
+#endif
-- 
2.5.3

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