Re: [PATCH v3 27/27] ARM: dts: omap3: Fix gpmc and NAND nodes

[Roger Quadros]

On 13/10/15 03:43, Tony Lindgren wrote:
> * Roger Quadros <rogerq@xxxxxx> [150918 08:00]:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller and interrupt-controller properties.
>>
>> With this the interrupt parent of NAND node changes so fix it
>> accordingly.
> ...
>> --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>> +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi
>> @@ -35,11 +35,14 @@
>>  };
>>  
>>  &gpmc {
>> -	ranges = <0 0 0x00000000 0x1000000>;	/* CS0: 16MB for NAND */
>> +	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
>>  
>>  	nand@0,0 {
>> -		linux,mtd-name = "micron,mt29f4g16abbda3w";
>> +		compatible = "ti,omap2-nand";
>>  		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
>> +		interrupt-parent = <&intc>;
>> +		interrupts = <20>;
>> +		linux,mtd-name = "micron,mt29f4g16abbda3w";
>>  		nand-bus-width = <16>;
>>  		ti,nand-ecc-opt = "bch8";
>>  		gpmc,sync-clk-ps = <0>;
> 
> At least torpedo breaks for NFSroot as NAND now overlaps with
> Ethernet.. What's the policy you have for moving the addresses
> around?

For OMAP3 I intended to use 0x30000000 for NAND but incorrectly
used 0x08000000 for the torpedo.

Does setting it to 0x30000000 work? If not what is the original
NAND address for this board?

> 
> There may be other similar cases to check too.

Just checked that all other OMAP3 boards I've set to 0x30000000
if they were 0x0.

cheers,
-roger
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