Re: [RFC PATCH] qspinlock: Improve performance by reducing load instruction rollback

[Ling Ma]

>
> I did see some performance improvement when I used your test program on a
> Haswell-EX system. It seems like the use of cmpxchg has forced the changed
> memory values to be visible to other processors earlier. I also ran your
> test on an older machine with Westmere-EX processors. This time, I didn't
> see any performance improvement. In fact, your change actually make it a
> tiny bit slower. So the benefit of your patch can be highly processor
> sensitive.
>
> As other architectures like ARM & AA64 are going to adopt qspinlock in the
> near future, we will also need to make sure that it won't cause a regression
> there. So I don't see your patch has a big chance of being merged upstream
> unless you can provide a real world workload that can benefit from your
> patch. Even then, proving that it won't cause regression in other processors
> or architectures can be tedious.
>

The optimization will be closely related with CPU arch and cache
coherence implementation.
so we will test it for real world workload on Haswell, and send out the result.

Thanks
Ling
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