[PATCH V2 1/2] x86/mcheck: Add Scalable MCA cpuid bit

[Aravind Gopalakrishnan]

Scalable MCA (SMCA) is a new feature in AMD Fam17h
processors which indicates presence of MCA extensions.

MCA extensions expands existing register space for the
MCE banks and also introduces a new MSR range to
accommodate new banks. Future additions to AMD MCE code
will first need to detect if SMCA is enabled before
enabling the new features.

Adding code to detect if it SMCA is enabled in this patch
and store that info in mce_vendor_flags structure.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@xxxxxxx>
---
 arch/x86/include/asm/mce.h       | 13 ++++++++++++-
 arch/x86/kernel/cpu/mcheck/mce.c |  2 ++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2dbc0bf..63307b5 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -135,7 +135,18 @@ struct mce_vendor_flags {
 			 * in HW and deferred error interrupts.
 			 */
 			succor		: 1,
-			__reserved_0	: 62;
+
+			/*
+			 * Scalable MCA: This bit indicates support for MCAX
+			 * (MCA EXtensions) which expands the register space
+			 * for each MCA bank and also increases number of
+			 * banks. Also, to accommodate the new banks and
+			 * registers, the MCA register space is moved to a new
+			 * MSR range
+			 */
+			smca		: 1,
+
+			__reserved_0	: 61;
 };
 extern struct mce_vendor_flags mce_flags;
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 17b5ec6..3d631c4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 		mce_amd_feature_init(c);
 		mce_flags.overflow_recov = !!(ebx & BIT(0));
 		mce_flags.succor	 = !!(ebx & BIT(1));
+		mce_flags.smca		 = !!(ebx & BIT(3));
+
 		break;
 		}
 
-- 
2.6.1

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