Re: [PATCH v2 0/3] let Marvell Berlin SoCs make use of the best delay timer

From: Daniel Lezcano
Date: Wed Nov 04 2015 - 04:47:00 EST

On 11/03/2015 03:28 PM, Jisheng Zhang wrote:
In case there are several possible delay timers, we purely base the
selection on the frequency, which is suboptimal in some cases. Take
one Marvell Berlin platform for example: we have arch timer and dw-apb
timer. The arch timer freq is 25MHZ while the dw-apb timer freq is
100MHZ, current selection would choose the dw-apb timer. But the dw
apb timer is on the APB bus while arch timer sits in CPU, the cost
of accessing the apb timer is higher than the arch timer.

This series firstly modifies register_current_timer_delay() to choose
the highest rating delay timer: use the rating as a primary indication
and fall back to comparing the frequency if the rating is not set or
the same. Then we set the arch_delay_timer rating as 400, finally
Implement ARM delay timer for the dw_apb_timer and set its rating as 300.

Hi Jisheng, Arnd,

I don't feel comfortable with the rating / freq think. I am afraid this approach based on heuristic will bring a lot of complexity and workarounds in the code for a small benefit.

Why don't we define a DT entry for the delay timer ? So we delegate the choice to the platform DT definition.

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