Re: [PATCH V15 04/11] x86/intel_rdt: Add support for Cache Allocation detection
From: Luiz Capitulino
Date: Wed Nov 04 2015 - 09:51:55 EST
On Thu, 1 Oct 2015 23:09:38 -0700
Fenghua Yu <fenghua.yu@xxxxxxxxx> wrote:
> This patch includes CPUID enumeration routines for Cache allocation and
> new values to track resources to the cpuinfo_x86 structure.
>
> Cache allocation provides a way for the Software (OS/VMM) to restrict
> cache allocation to a defined 'subset' of cache which may be overlapping
> with other 'subsets'. This feature is used when allocating a line in
> cache ie when pulling new data into the cache. The programming of the
> hardware is done via programming MSRs (model specific registers).
>
> Signed-off-by: Vikas Shivappa <vikas.shivappa@xxxxxxxxxxxxxxx>
> Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx>
> ---
> arch/x86/include/asm/cpufeature.h | 6 +++++-
> arch/x86/include/asm/processor.h | 3 +++
> arch/x86/kernel/cpu/Makefile | 1 +
> arch/x86/kernel/cpu/common.c | 15 +++++++++++++++
> arch/x86/kernel/cpu/intel_rdt.c | 40 +++++++++++++++++++++++++++++++++++++++
> init/Kconfig | 12 ++++++++++++
> 6 files changed, 76 insertions(+), 1 deletion(-)
> create mode 100644 arch/x86/kernel/cpu/intel_rdt.c
>
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index e6cf2ad..4e93006 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -12,7 +12,7 @@
> #include <asm/disabled-features.h>
> #endif
>
> -#define NCAPINTS 13 /* N 32-bit words worth of info */
> +#define NCAPINTS 14 /* N 32-bit words worth of info */
> #define NBUGINTS 1 /* N 32-bit bug flags */
>
> /*
> @@ -231,6 +231,7 @@
> #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
> #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
> #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
> +#define X86_FEATURE_RDT ( 9*32+15) /* Resource Allocation */
> #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
> #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
> #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
> @@ -255,6 +256,9 @@
> /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
> #define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
>
> +/* Intel-defined CPU features, CPUID level 0x00000010:0 (ebx), word 13 */
> +#define X86_FEATURE_CAT_L3 (13*32 + 1) /* Cache Allocation L3 */
> +
> /*
> * BUG word(s)
> */
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 19577dd..b932ec4 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -120,6 +120,9 @@ struct cpuinfo_x86 {
> int x86_cache_occ_scale; /* scale to bytes */
> int x86_power;
> unsigned long loops_per_jiffy;
> + /* Cache Allocation values: */
> + u16 x86_cache_max_cbm_len;
> + u16 x86_cache_max_closid;
> /* cpuid returned max cores value: */
> u16 x86_max_cores;
> u16 apicid;
> diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
> index 4eb065c..5e873c7 100644
> --- a/arch/x86/kernel/cpu/Makefile
> +++ b/arch/x86/kernel/cpu/Makefile
> @@ -50,6 +50,7 @@ obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_msr.o
> obj-$(CONFIG_CPU_SUP_AMD) += perf_event_msr.o
> endif
>
> +obj-$(CONFIG_INTEL_RDT) += intel_rdt.o
>
> obj-$(CONFIG_X86_MCE) += mcheck/
> obj-$(CONFIG_MTRR) += mtrr/
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index de22ea7..026a416 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -654,6 +654,21 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
> }
> }
>
> + /* Additional Intel-defined flags: level 0x00000010 */
> + if (c->cpuid_level >= 0x00000010) {
> + u32 eax, ebx, ecx, edx;
> +
> + cpuid_count(0x00000010, 0, &eax, &ebx, &ecx, &edx);
> + c->x86_capability[13] = ebx;
> +
> + if (cpu_has(c, X86_FEATURE_CAT_L3)) {
> +
> + cpuid_count(0x00000010, 1, &eax, &ebx, &ecx, &edx);
> + c->x86_cache_max_closid = edx + 1;
> + c->x86_cache_max_cbm_len = eax + 1;
> + }
Both registers contain reserved bits. Shouldn't they be masked
out as recommended by the SDM?
Also, I'm surprised you're not storing ebx. How is it going to be
possible to create a CBM to fully isolate L3 entries without
knowing which entries are being used by the hardware?
> + }
> +
> /* AMD-defined flags: level 0x80000001 */
> xlvl = cpuid_eax(0x80000000);
> c->extended_cpuid_level = xlvl;
> diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
> new file mode 100644
> index 0000000..f49e970
> --- /dev/null
> +++ b/arch/x86/kernel/cpu/intel_rdt.c
> @@ -0,0 +1,40 @@
> +/*
> + * Resource Director Technology(RDT)
> + * - Cache Allocation code.
> + *
> + * Copyright (C) 2014 Intel Corporation
> + *
> + * 2015-05-25 Written by
> + * Vikas Shivappa <vikas.shivappa@xxxxxxxxx>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * More information about RDT be found in the Intel (R) x86 Architecture
> + * Software Developer Manual June 2015, volume 3, section 17.15.
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +
> +static int __init intel_rdt_late_init(void)
> +{
> + struct cpuinfo_x86 *c = &boot_cpu_data;
> +
> + if (!cpu_has(c, X86_FEATURE_CAT_L3))
> + return -ENODEV;
> +
> + pr_info("Intel cache allocation detected\n");
> +
> + return 0;
> +}
> +
> +late_initcall(intel_rdt_late_init);
> diff --git a/init/Kconfig b/init/Kconfig
> index c24b6f7..9fe3f11 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -938,6 +938,18 @@ menuconfig CGROUPS
>
> Say N if unsure.
>
> +config INTEL_RDT
> + bool "Intel Resource Director Technology support"
> + depends on X86_64 && CPU_SUP_INTEL
> + help
> + This option provides support for Cache allocation which is a
> + sub-feature of Intel Resource Director Technology(RDT).
> + Current implementation supports L3 cache allocation.
> + Using this feature a user can specify the amount of L3 cache space
> + into which an application can fill.
> +
> + Say N if unsure.
> +
> if CGROUPS
>
> config CGROUP_DEBUG
--
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