Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

From: Gratian Crisan
Date: Tue Nov 17 2015 - 12:04:00 EST

Dave Hansen writes:

> On 11/09/2015 02:02 PM, Peter Zijlstra wrote:
>> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.crisan@xxxxxx wrote:
>>> The Intel Xeon E5 processor family suffers from errata[1] BT81:
>>> +#ifdef CONFIG_X86_TSC
>>> + /*
>>> + * Xeon E5 BT81 errata: TSC is not affected by warm reset.
>>> + * The TSC registers for CPUs other than CPU0 are not cleared by a warm
>>> + * reset resulting in a constant offset error.
>>> + */
>>> + if ((c->x86 == 6) && (c->x86_model == 0x3f))
>>> + set_cpu_bug(c, X86_BUG_TSC_OFFSET);
>>> +#endif
>> That's hardly a family, that's just one, Haswell server.
> How did you come up with that x86_model? The document you linked to
> claimes that "Extended Model" is 0010b and "Model Number" is 1101b, so
> the x86_model you are looking for should be 0x2d.

Apologies. I've messed up. The observed behavior seemed to match the
errata and it was a Xeon E5. I've used the model number I read of the
machine exhibiting the behavior w/o properly matching it with the model
number in the errata.

In the meantime Peter Zijlstra pointed me in the right direction i.e. it
looks like the BIOS is changing the TSC_ADJUST for CPU0 but not any of
the other ones. I'll sort it out with our BIOS guys and drop this patch.

Sorry again for the confusion.
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