Re: [PATCH 02/25] serial: sh-sci: Update DT binding documentation for BRG support

[Laurent Pinchart]

Hi Geert,

Thank you for the patch.

On Thursday 19 November 2015 19:38:41 Geert Uytterhoeven wrote:
> Amend the DT bindings to include the optional clock sources for the Baud
> Rate Generator for External Clock (BRG), as found on some SCIF variants
> and on HSCIF.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> ---
>  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index
> 8efc9b6f35637fbb..ae907e39b11c2a5a 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
> @@ -46,6 +46,12 @@ Required properties:
>      On (H)SCI(F) and some SCIFA, an additional clock may be specified:
>        - "hsck" for the optional external clock input (on HSCIF),
>        - "sck" for the optional external clock input (on other variants).
> +    On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
> +    (some SCIF and HSCIF), additional clocks may be specified:
> +      - "int_clk" for the optional internal clock source for the frequency
> +	divider (typically the (AXI or SHwy) bus clock),

Isn't this always the same clock as the SCIF functional clock ?

> +      - "scif_clk" for the optional external clock source for the frequency
> +	divider (SCIF_CLK).
> 
>  Note: Each enabled SCIx UART should have an alias correctly numbered in the
> "aliases" node.

-- 
Regards,

Laurent Pinchart

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