Re: [linux-sunxi] [PATCH] spi: dts: sun4i: Add support for inter-word wait cycles using the SPI Wait Clock Register

From: Julian Calaby
Date: Fri Nov 20 2015 - 05:12:33 EST

Hi Marcus,

On Fri, Nov 20, 2015 at 7:45 PM, Marcus Weseloh <mweseloh42@xxxxxxxxx> wrote:
> Hi Julian,
> 2015-11-19 23:59 GMT+01:00 Julian Calaby <julian.calaby@xxxxxxxxx>:
>> Should you possibly hide the 3 clock periods from the user?
>> I.e. they set whatever they want for the wdelay, we set it to the
>> closest number we can that's greater or equal to what they ask for.
> That's a good idea and much better than having to remember to subtract
> 3 cycles from the desired wait time!
> But it would mean that this magic number becomes part of the driver
> code. I have found no official documentation that mentions those
> additional cycles. While I have checked many different transmission
> speeds using both CDR1 and CDR2 divider configurations, there is still
> the possibility that the behaviour changes with weird SPI module
> configurations... And I've only tested it on A20 hardware. So it would
> be great if somebody else with access to A10 hardware and an
> oscilloscope could check if we have a consistent 3 cycle overhead.

Having magic numbers is kind-of a drivers' job. (and the wdelay should
arguably be a core-spi thing, not a sunxi thing, but that's a separate

If it is different for other SoCs, then you might have to move that
constant somewhere else and introduce new compatible strings for them.


Julian Calaby

Email: julian.calaby@xxxxxxxxx
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